DP83865 datasheet(49/86 Pages) NSC

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4.0 Functional Description

The DP83865 is a full featured 10/100/1000 Ethernet Phys-

ical layer (PHY) chip. It consists of a digital 10/100/1000

Mb/s core with a common TP interface. It also has a com-

bined versitle MAC interface that is capable of interfacing

with MII and GMII controller interfaces. In this section, the

following topics are covered:

— 1000BASE-T PCS Transmitter

— 1000BASE-T PMA Transmitter

— 1000BASE-T PMA Receiver

— 1000BASE-T PCS Receiver

— Gigabit MII (GMII)

— Reduced GMII (RGMII)

— 10BASE-T and 100BASE-TX Transmitter

— 10BASE-T and 100BASE-TX Receiver

— Media Dependent Interface (MII)

The 1000BASE-T transceiver includes PCS (Physical Cod-

ing Sublayer) Transmitter, PMA (Physical Medium Attach-

ment) Transmitter, PMA Receiver and PCS Receiver. The

1000BASE-T functional block diagram is shown in section

“ Block Diagram” on page 2.

4.1 1000BASE-T PCS Transmitter

The PCS transmitter comprises several functional blocks

that convert the 8-bit TXDn data from the GMII to PAM-5

symbols passed onto the PMA function. The block diagram

of the PCS transmitter data path in Figure 2 provides an

overview of each of the architecture within the PCS trans-

mitter.

The PCS transmitter consists of eight sub blocks:

— LFSR (Linear Feedback Shift Register)

— Data scrambler and symbol sign scrambler word gener-

ator

— Scrambler bit generator

—Data scrambler

— Convolutional encoder

— Bit-to-symbol quinary symbol mapping

— Sign scrambler nibble generator

— Symbol sign scrambler

The requirements for the PCS transmit functionality are

also defined in the IEEE 802.3ab specification section

40.3.1.3 “PCS Transmit function”.

4.1.1 Linear Feedback Shift Register (LFSR)

The side-stream scrambler function uses a LFSR imple-

menting one of two equations based on the mode of opera-

tion, i.e., a master or a slave. For master operation, the

equation is

gM(x) = 1 + x

13 + x33

For slave operation, the equation is

gS(x) = 1 + x

20 + x33

The 33-bit data output, Scrn[32:0], of this block is then fed

to the data scrambler and symbol sign scrambler word gen-

erator.

4.1.2 Data and Symbol Sign Scrambler Word Generator

The word generator uses the Scrn[32:0] to generate further

scrambled values. The following signals are generated:

Sxn[3:0], Syn[3:0], and Sgn[3:0].

The 4-bit Sxn[3:0] and Syn[3:0] values are then sent to the

scrambler bit generator. The 4-bit Sgn[3:0] sign values are

provided to the sign scrambler nibble generator.

4.1.3 Scrambler Bit Generator

This sub block uses the Sxn and Syn signals along with the

tx_mode and tx_enable signals to generate the Scn[7:0],

that is further scrambled based on the condition of the

tx_mode and tx_enable signal. The tx_mode signal indi-

cates sending idles (SEND_I), sending zeros (SEND_Z) or

sending idles/data (SEND_N). The tx_mode signal is gen-

erated by the micro controller function. The tx_enable sig-

nal is either asserted to indicate data transmission is

occurring or deasserted when there is no data transmis-

sion. The PCS Data Transmission Enable state machine

generates the tx_enable signal.

The 8-bit Scn[7:0] signals are then passed onto the data

scrambler functional block.

4.1.4 Data Scrambler

The Data Scrambler generates scrambled data by accept-

ing the TxDn[7:0] data from the GMII and scrambling it

based on various inputs.

The data scrambler generates the 8-bit Sdn[7:0] value,

which scrambles the TxDn data based primarily on the Scn

values and the accompanying control signals.

All 8-bits of Sdn[7:0] are passed onto the bit-to-quinary

symbol mapping block, while 2-bits, Sdn[7:6], are fed into

the convolutional encoder.

4.1.5 Convolutional Encoder

The encoder uses Sdn[7:6] bits and tx_enable to generate

an additional data bit, which is called Sdn[8].

The one clock delayed versions csn-1[1:0] are passed to

the data scrambler block. This Sdn[8] bit is then passed to

the bit-to-symbol quinary symbol mapping function.

4.1.6 Bit-to-Symbol Quinary Symbol Mapping

This block implements the IEEE 802.3ab specification

Tables 40-1 and 40-2 Bit-to-Symbol Mapping for even and

odd subsets. It takes the 9-bit Sdn[8:0] data and converts it

to the appropriate quinary symbols as defined by the

tables.

The output of this block generates the TAn, TBn, TCn, and

TDn symbols that passed onto the symbol sign scrambler.

4.1.7 Sign Scrambler Nibble Generator

Sign Scrambler Nibble Generator performs some further

scrambling of the sign values Sgn[3:0] that are generated

by the data and symbol sign scrambler word generator.

The sign scrambling is dependent on the tx_enable signal.

The SnAn, SnBn, SnCn, and SnDn outputs are then passed

onto the symbol sign scrambler function.

DP83865 Datasheet(PDF) 49 Page - National Semiconductor (TI)

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