DP83865 datasheet(76/86 Pages) NSC

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6.0 Electrical Specifications (Continued)

6.5 RGMII Timing

6.5.1 Transmit and Receive Multiplexing and Timing

TX [3:0]

TskewT

TXEN_ER

TCK

TXD[3:0]

TXD[7:4]

TX_EN

TX_ER

TXD[3:0]

TXD[7:4]

TX_EN

TX_ER

Tcyc

Parameter

Description

Notes

Min

Typ

Max

Units

TskewT

TX to Clock skew (at receiver, PHY), HP mode

Note 1

1.0

2.0

TskewT

TX to Clock skew (at receiver, PHY), 3COM mode

Note 4

-900

900

TskewR

RX to Clock skew (at transmitter, PHY), HP mode

Note 4

-500

500

TsetupR

RX to Clock setup (at transmitter, PHY), 3COM mode

Note 4

1.4

TholdR

RX to Clock hold (at transmitter, PHY), 3COM mode

Note 4

1.2

Tcyc

Clock Period

Note 2, 4

7.2

8.8

TDuty_G

Duty Cycle for gigabit

Note 3

TDuty_T

Duty Cycle for 10/100 BASE-T

Note 3

Tr/Tf

Rise/Fall Time (20 -80%)

Note 4

1.0

Note 1: The PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns is added to the associated clock signal.

Note 2: For 10 Mbps and 100 Mbps, Tcyc will scale to 400ns +-40ns and 40ns +-4ns.

Note 3: Duty cycle may be stretched or shrunk during speed changes or while transitioning to a received packet’s clock domain as long as minimum duty

cycle is not violated and stretching occurs for no more that three Tcyc of the lowest speed transitioned between.

Note 4: Guaranteed by design. Not tested.

RCK

RX [3:0]

RXDV_ER

TskewR TsetupR

RXD[3:0]

RXD[7:4]

RX_DV

RX_ER

RXD[3:0]

RXD[7:4]

RX_DV

RX_ER

Tcyc

TholdR

DP83865 Datasheet(PDF) 76 Page - National Semiconductor (TI)

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