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DP83865 Datasheet(PDF) 12 Page - National Semiconductor (TI) |
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DP83865 Datasheet(HTML) 12 Page - National Semiconductor (TI) |
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12 / 86 page  www.national.com 12 1.0 Pin Description (Continued) 1.10 Pin Assignments in the Pin Number Order Table 1. Pin # Data Sheet Pin Name Type Connection / Comment 1 NON_IEEE_STRAP Strap Non IEEE Compliant Mode Enable: Use a 2k Ω pull-up resistor to enable. Leave open to disable. 2 RESERVED Reserved Reserved: Leave floating. 3 INTERRUPT Output INTERRUPT: Connect to MAC or management IC. This is a tri-state pin and requires an external 2k Ω pull-up resistor if the pin is used. 4IO_VDD Power I/O VDD: (Digital) Connect to 2.5V or 3.3V. The VDD_SEL pin must be tied accordingly. 5 VSS Ground Ground: Connect to common ground plane. 6 TX_TCLK Output Transmit Test Clock: See section “1.9 Special Connect Pins” on page 11. 7 ACTIVITY_LED / SPEED0_STRAP Strap / Output Activity LED / SPEED0 Select: See section “5.9 LED/Strapping Option” on page 67 on how to connect this pin for speed selection and ACTIVITY_LED function. 8 LINK10_LED / RLED/SPEED1_STRAP Strap / Output 10M Link LED / RLED / SPEED1: See section “5.9 LED/Strapping Option” on page 67 on how to connect this pin for speed selection and LINK10_LED function. 9 LINK100_LED / DUPLEX_STRAP Strap / Output 100M Link LED / Duplex Select: See section “5.9 LED/Strapping Option” on page 67 on how to connect this pin for Duplex selection and 100_LED function. 10 LINK1000_LED / AN_EN_STRAP Strap / Output 1000M Link LED / Auto-Neg. Select: See sec- tion “5.9 LED/Strapping Option” on page 67 on how to connect this pin for Auto-negotiation con- figuration and 1000_LED function. 11 CORE_VDD Power Core VDD: (Digital) Connect to 1.8V. 12 VSS Ground Ground: Connect to common ground plane. 13 DUPLEX_LED / PHYADDR0_STRAP Strap / Output Duplex LED / PHY Address 0: See section “5.9 LED/Strapping Option” on page 67 on how to connect this pin for PHY address configura- tion and DUPLEX_LED function. 14 PHYADDR1_STRAP Strap PHY Address 1: See section “5.9 LED/Strapping Option” on page 67 on how to connect this pin. 15 IO_VDD Power I/O VDD: (Digital) Connect to 2.5V or 3.3V. The VDD_SEL pin must be tied accordingly. 16 VSS Ground Ground: Connect to common ground plane. 17 PHYADDR2_STRAP Strap PHY Address 2: See section “5.9 LED/Strapping Option” on page 67 on how to connect this pin 18 PHYADDR3_STRAP Strap PHY Address 3: See section “5.9 LED/Strapping Option” on page 67 on how to connect this pin 19 CORE_VDD Power Core VDD: (Digital) Connect to 1.8V. 20 VSS Gound Ground: Connect to common ground plane. 21 IO_VDD Power I/O VDD: (Digital) Connect to 2.5V or 3.3V. The VDD_SEL pin must be tied accordingly. 22 VSS Ground Ground: Connect to common ground plane. |
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