PC87591L datasheet(279/437 Pages) NSC

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5.0 Host Controller Interface Modules (Continued)

Revision 1.07

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Status Read

Both the host and the core can read the status of the KBC data buffers. Bits 2 and 4 to 7 can be written by the core. The

host processor should read address 6416 to obtain the contents of the Status register. The core software can obtain this

information by reading/writing the HIKMST register. The format of the Status register is identical for both the host and the

core (see “Host Interface Keyboard/Mouse Status Register (HIKMST)” on page 284).

Host Data Write to Host Interface Keyboard/Mouse Channel

The data buffer has two latches; one serves as an input buffer and the other as an output buffer. When writing to address

6016 or 6416, the following sequence of events occurs: the data is written to the Data In latch (DBBIN), IBF bit in the Status

register is set and bit 3 (A2) in the Status register indicates to the core which address (command or data) was written to.

When writing to address 6016 (legacy A2=0), bit 3 of the Status register is cleared. When writing to address 6416 (legacy

A2=1), bit 3 of the Status register is set.

The core identifies that data is present in the input buffer by either polling IBF bit of the Status register or acknowledging an

interrupt when the input buffer interrupt is enabled (IBFCIE in HICTRL register is set to 1).

When the input buffer is full, reading the Status register identifies which address was written to (i.e., check A2 of HIKMST

register). The core can then read the data from the input buffer (HIKMDI). The IBF status bit is cleared when the data input

buffer is read by the core.

Host Data Read from Host Interface Keyboard/Mouse Channel

The output data latch (DBBOUT) is written by the core when it needs to send data to the host. The OBF flag in the Status

register (OBF in HIKMST register) is set to indicate that data is available in DBBOUT. DBBOUT should be written only when

this bit is cleared.

The PC87591x supports polling and interrupt communication schemes with the host. Both Keyboard interrupt (IRQ1) and

Mouse interrupt (IRQ12) are supported.

The core firmware writes to HIKDO register data addressed to the keyboard driver (i.e., generate IRQ1). A write to HIKDO

stores the data to DBBOUT and sets OBF bit. If the IRQ1 interrupt is enabled (OBFKIE in HICTRL register is set to 1), it is

also sent according to the interrupt mode (IRQM field and IRQNPOL bit in HIIRQC register).

The core firmware writes data addressed to the mouse driver (IRQ12) to HIMDO register. A write to HIMDO stores the data

in DBBOUT and sets OBF bit. If the IRQ12 interrupt is enabled (OBFMIE in HICTRL is set to 1); the IRQ12 interrupt is also

sent according to the interrupt mode (IRQM field and IRQNPOL bit in HIIRQC register).

DBBIN

DBBOUT

STATUS

D0-7

Host-WR-Data-Buffer

Host-RD-Data-Buffer

WR-Mouse

WR-KBD

RD-Input

Buffer

Input Buffer

Full

Output Buffer

Empty

Interrupts to the Core

(IRQ1)

Peripheral Bus

SIB Bus

Interrupts to the Host Processor

Figure 94. Host Interface Keyboard/Mouse Channel (Ports 60,64) Block Diagram

Keyboard

Mouse

(IRQ12)

through SuperI/O Configuration

Interrupt Request

PC87591L Datasheet(PDF) 279 Page - National Semiconductor (TI)

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