PC87591L datasheet(282/437 Pages) NSC

282 / 437 page

5.0 Host Controller Interface Modules (Continued)

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282

Revision 1.07

5.1.4

Core Interface Registers

Some register bits affect PM channel 1 to achieve firmware compatibility with the PC87570.

For a summary of the abbreviations used for Register Type, see Section 2 on page 34.

Core Interface Register Map

Host Interface Control Register (HICTRL)

The HICTRL is used in setting host interface mechanism options. On reset, non-reserved bits of HICTRL are cleared.

Location: 00 FEA016

Type: R/W

Mnemonic

Type

HICTRL

Host Interface Control

R/W

HIIRQC

Host Interface IRQ Control

R/W

HIKMST

Host Interface Keyboard/Mouse Status

R/W

HIKDO

Host Interface Keyboard Data Out Buffer

HIMDO

Host Interface Mouse Data Out Buffer

HIKMDI

Host Interface Keyboard/Mouse Data In Buffer

Bit

76543210

Name

Reserved

PMICIE

PMIOCIE

PMIHIE

IBFCIE

OBECIE

OBFMIE

OBFKIE

Reset

00000000

Bit

Description

OBFKIE (Output Buffer Full Keyboard Interrupt Enable).

0: IRQ1 is controlled by IRQ1B bit in HIIRQC register

1: Enables the Output Buffer Full interrupt to the keyboard driver of the host processor (IRQ1). The interrupt is

triggered by a core write to HIKDO register and sent according to IRQM field and IRQNPOL bit in HIIRQC reg-

ister.

OBFMIE (Output Buffer Full Mouse Interrupt Enable).

0: IRQ12 is controlled by IRQ12B bit in HIIRQC register

1: Enables the Output Buffer Full interrupt to the mouse driver in the host processor (IRQ12). The interrupt is trig-

gered by the core write to HIMDO register and sent according to IRQM field and IRQNPOL bit in HIIRQC reg-

ister.

OBECIE (Output Buffer Empty Core Interrupt Enable).

0: Interrupt signal is low

1: Enables the Output Buffer Empty interrupt to the core ICU for the keyboard/mouse channel. The interrupt signal

is active when the output buffer is empty (i.e., the interrupt signal is set (1) when OBF bit is cleared).

IBFCIE (Input Buffer Full Core Interrupt Enable).

0: Interrupt signal is low

1: Enables the Input Buffer Full interrupt to the core ICU for the keyboard/mouse channel. The interrupt signal is

active when the input buffer is full (i.e., the interrupt signal is set (1) when IBF bit is set).

PMIHIE (PMI Channel 1 Host Interrupt Enable).

0: IRQ11 is controlled by IRQ11B bit in HIIRQC register

1: Enables the Output Buffer Full interrupt of PM channel 1 in PC87570 Compatible mode, to drive the host pro-

cessor interrupt. The interrupt is noted as IRQ11 and may be routed to any of the IRQs, to SMI or to the SCI

events. The interrupt is triggered by a core write to HIPM0DO register and sent according to IRQM field and

IRQNPOL bit in HIIRQC register.

PC87591L Datasheet(PDF) 282 Page - National Semiconductor (TI)

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