PC87591L datasheet(280/437 Pages) NSC

280 / 437 page

5.0 Host Controller Interface Modules (Continued)

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The host processor identifies that data is present in the output buffer by either polling the Status register (reading address

6416) or responding to IRQ1 or IRQ12. When this data is available, the host can read it using a read operation from address

6016. Reading from address 6016 clears the OBF flag. In addition, when the host interrupt is in level mode (IRQM in HIIRQC

The core can read OBF bit to identify when the output buffer is empty and ready for a new data transfer. When the Output

Buffer Empty interrupt to the core is enabled (OBECIE in HICTRL register is set to 1), the interrupt signal to the ICU is set

high if the output buffer is empty (OBF=0).

5.1.3

Host Interface Registers

The module has four registers, described below. The base address for each may be configured individually. For legacy op-

eration, they should be configured to 6016 and 6416 (see Section 6.1.10 on page 348).

For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 34.

Host Interface Register Map

Data Out Buffer Register (DBBOUT, Legacy 6016)

This register allows the host to read DBBOUT register while clearing OBF bit in the Status register. If the host interrupts are

level (IRQM in HIIRQC register is 0002), the interrupt is de-asserted. If the core interrupt on output buffer empty is enabled

(OBECIE in HICTRL register is set to 1), reading this register asserts it (high).

Location: As defined in LDN 0616 registers, index 6016 and 6116

Type: R

Offset

Mnemonic

Type

6016

DBBOUT

Data Out Buffer

6416

STATUS

Status

6016

DBBIN

Data In Buffer

6416

COMAND

Command In Buffer

Bit

76543210

Name

Keyboard/Mouse DBBOUT Data

Bit

Description

7-0

Keyboard/Mouse DBBOUT Data.

PC87591L Datasheet(PDF) 280 Page - National Semiconductor (TI)

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