PC87591L datasheet(283/437 Pages) NSC

283 / 437 page

5.0 Host Controller Interface Modules (Continued)

Revision 1.07

283

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Host Interface IRQ Control Register (HIIRQC)

The HIIRQC register controls the IRQ signals mode of operation. On reset, HIIRQC is set to 0716.

Location: 00 FEA216

Type: R/W

PMOCIE (PM Channel 1 Output Buffer Empty Core Interrupt Enable).

0: Interrupt signal is low

1: Enables the PM Output Buffer Empty interrupt to the core ICU for PM channel 1 in PC87570 Compatible mode.

The interrupt signal is active when the output buffer is empty (OBF bit is cleared in the PM channel status reg-

ister).

PMICIE (PM Channel 1 Input Buffer Full Core Interrupt Enable).

0: Interrupt signal is low

1: Enables the PM input buffer full interrupt to the core ICU for PM channel 1 in PC87570 Compatible mode. The

interrupt signal is active when the input buffer is full (IBF bit is set in the PM channel status register).

Reserved.

Bit

76543210

Name

Reserved

IRQNPOL

IRQM

IRQ11B

IRQ12B

IRQ1B

Reset

00000111

Bit

Description

IRQ1B (Host Interrupt Request 1 Control Bit). When the IRQ1 signal is conﬁgured for direct control by the

ﬁrmware (OBFKIE in HICTRL register is 0), IRQ1B bit is output to the IRQ1 signal. When read, IRQ1B bit

returns the current value of the IRQ1 pin. The IRQ1 signal value an be read regardless of the state of OBFKIE

bit.

IRQ12B (Host Interrupt Request 12 Control Bit). When the IRQ12 signal is conﬁgured for direct control by the

ﬁrmware (OBFMIE in HICTRL register is 0), IRQ12B bit is output to the IRQ12 signal. When read, IRQ12B bit

returns the current value of the IRQ12 pin. The IRQ12 signal value can be read regardless of the state of the

OBFMIE bit.

IRQ11B (Host Interrupt Request 11 Control Bit). When PM channel 1 is in PC87570 Compatible mode and

its host interrupt is configured for direct control by the firmware (PMHIE in HICTRL register is 0), IRQ11B bit is

output to the IRQ11 signal. When read, IRQ11B bit returns the current value of the IRQ11 signal. The IRQ11

signal value can be read regardless of the state of PMHIE bit; see Section 5.2 on page 285 for details about the

PM channel 1 interrupt scheme.

5-3

IRQM (IRQ Mode). Sets the hardware-controlled IRQ signals to work in Level or Pulse mode and deﬁnes the

pulse width in Pulse mode.

When IRQM = 0002, the IRQ signals function in Level mode. In this mode, when IRQNPOL = 0, the signal’s

default value is low, and a high level is set to issue an interrupt (the respective OBF is set).

When IRQM

≠ 0, the host interrupts are in Pulse mode. When IRQNPOL = 0, the signal’s default value is high

and toggles low to issue an interrupt (i.e., when the respective output buffer register is written). The pulse width

is as follows:

Bits

5 4 3

Pulse Width

0 0 0:

Level Interrupt

0 0 1:

1-Cycle Pulse

0 1 0:

2-Cycle Pulse

0 1 1:

4-Cycle Pulse

1 0 0:

8-Cycle Pulse

1 0 1:

16-Cycle Pulse

Other:

Reserved

Bit

Description

PC87591L Datasheet(PDF) 283 Page - National Semiconductor (TI)

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