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PC87591L Datasheet(PDF) 287 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # PC87591L
Description  LPC Mobile Embedded Controllers
PDF  437 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC87591L Datasheet(HTML) 287 Page - National Semiconductor (TI)

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5.0 Host Controller Interface Modules (Continued)
Revision 1.07
287
www.national.com
Table 43. Host Interface Registers to Host Processor Mapping
Core Interrupts
For each channel, the Host Interface module generates two level (high) interrupts to the core ICU (see Figure 96). The firm-
ware can use these for interrupt-driven control of the PM channels.
In PC87570 Compatible mode (EME in HIPMnCTL register is set to 0), interrupts are enabled using HICTRL register bits
PMOCIE and PMICIE for output buffer empty and input buffer full interrupts, respectively.
In Enhanced PM mode (EME in HIPMnCTL register is set to1), interrupts are enabled using HIPMnCTL register bits OBEIE
and IBFIE for output buffer empty and input buffer full interrupts, respectively.
Host Interrupt Generation Modes
The Host Interface module generates three types of interrupts to the host: regular IRQ, SMI and SCI. The interrupt schemes
are designed to meet ACPI requirements for host interrupts. Two interrupt modes are supported: PC87570 Compatible and
Enhanced PM.
PC87570 Compatible Mode
PC87570 Compatible mode uses the same method for IRQ generation as the PC87570. It is available only for PM channel 1
and is enabled when EME in HIPMnCTL register is set to 0. Figure 98 illustrates this scheme.
The host configuration module assigns host interrupts to IRQ numbers (see Section 6.1.13 on page 355). IRQ11 is used as
an example interrupt and for the signal naming (the actual interrupt number used is determined by the IRQ routing logic).
When hardware-driven IRQ11 is disabled (PMHIE in HICTRL register is cleared), the firmware can control the IRQ11 signal
by writing to the signal’s respective bit in HIIRQC register. When hardware-driven IRQ11 is enabled (PMHIE is set to 1),
interrupts to the host are generated according to the status of the OBF flag.
Port
Legacy
Address1
1. The legacy address serves as an example only. Do not assign the same address for both channels.
Configuration
Register Index
PM Internal Chip
Select
Type
Register
Name
Mnemonic
PM
Channel n
6216
Index 6016,6116
Data
Write
Data
DBBIN
6616
Index 6216,6316
Command/Status
Write
Command
DBBIN
6216
Index 6016,6116
Data
Read
Data
DBBOUT
6616
Index 6216,6316
Command/Status
Read
Status
STATUS
IBF bit (HIPMnST)
1
0
EME bit (HIPMnCTL)
OBF bit (HIPMnST)
PMOCIE bit (HICTRL)
OBEIE bit (HIPMnCTL)
1
0
PMICIE bit (HICTRL)
IBFIE bit (HIPMnCTL)
PMnOBE
Interrupt
PMnIBF
Interrupt
ICU
Figure 96. Core Interrupt Request for PM Channel n
EME bit (HIPMnCTL)



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