PC87591L datasheet(288/437 Pages) NSC

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5.0 Host Controller Interface Modules (Continued)

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Revision 1.07

In Normal Polarity mode (IRQNPOL in HIIRQC register is cleared), the PC87591x supports two types of interrupts: legacy

edge or legacy level. When an edge interrupt is selected (IRQM field in HIIRQC register is set to a value other than 0), the

interrupt signal default value is high (1). When an interrupt signal must be sent (i.e., OBF flag is set), a negative pulse is

generated. The pulse width is determined by the same field, IRQM, that selects the edge interrupt.

When a level interrupt is selected (IRQM in HIIRQC register is cleared), the interrupt signal is usually low (0). It is asserted

(1) to indicate that the respective OBF flag has been set. The signal is de-asserted (0) when the output buffer is read (i.e.,

OBF flag is cleared).

In Negative Polarity mode (IRQNPOL in HIIRQC register is set to 1), IRQ signal behavior is inverted from the behavior de-

scribed for normal polarity.

The PC87591x firmware can read the value of the IRQ11 signal by performing a read operation of IRQ11B bit in HIIRQC

The core can also control the routing of interrupts generated by the PM channel to one of the following:

●

IRQ signal, when IRQE bit in HIPMnIE register is set

●

SMI output, when SMIE bit in HIPMnIE register is set

●

SCI event, using the SCIEC output, when SCIE bit in HIPMnIE register is set.

The core firmware should not enable more than one of these interrupts simultaneously. It should also update ST0 and ST1

bits to indicate the type of host interrupt used.

Enhanced PM Mode

Enhanced PM mode is available for both PM channels. It is enabled when EME in HIPMnCTL register is set to 1. Figure 98

illustrates interrupt generation in this mode.

Either IRQ, SMI or SCI interrupts may be generated under software control or by using hardware. Using hardware reduces

software overhead and simplifies procedures.

The mechanism that generates the IRQ is identical to that used in PC87570 Compatible mode. To enable identical control

of both channels, the bits that are used for channel 1 are separated from the keyboard/mouse channel’s registers; see

Figure 98 for bit usage.

IRQE in HIPMnIE register determines if an IRQ is sent from PM Channel n.

Enhanced PM mode supports direct generation of SCI and SMI on core writes to the Data output buffer and generation of

SCI on core reading of the Data Input buffer. The core decides whether to generate an interrupt and which type of interrupt

to generate by selecting the data register address in use.

When data is written to HIPMnDO register, the OBF flag in HIPMnST register is set and neither SMI nor SCI is generated.

Hardware

IRQM field (HIIRQ)

Interrupt

IRQNPOL bit (HIIRQC)

IRQ11B bit (HIIRQC)

PMHIE bit (HICTRL)

IRQ11B bit (HIIRQC)

(Part of SuperI/O

Configuration

Module)

IRQ Routing

and Polarity

IRQ

Serializer

IRQE bit (HIPMnIE)

SMIE bit (HIPMnIE)

SCIE bit (HIPMnIE)

Gathering

SMI Source

Gathering

SCI Source

SMI

ECSCI

Figure 97. IRQ, SCI and SMI Control in PC87570 Compatible Mode (PM Channel 1 Only)

OBF

SMIPOL bit (HIPMnIC)

SCIPOL bit (HIPMnCTL)

(write)

(read)

(Level or Edge)

(Polarity)

(Hardware or Firmware)

PC87591L Datasheet(PDF) 288 Page - National Semiconductor (TI)

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