PC87591L datasheet(291/437 Pages) NSC

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5.0 Host Controller Interface Modules (Continued)

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Core PM Register Map

Host Interface PM n Status Register (HIPMnST)

The HIPMnST register contains the status of the host interface PM channel buffers (DBBIN and DBBOUT). It also provides

a means for the PC87591x to send status bits to the host. This register is read by a host processor read operation from ad-

dress 6616. HIPMnST is cleared on reset.

Location: Channel 1 - 00 FEAC16

Channel 2 - 00 FEBE16

Type: Varies per bit

Mnemonic

Type

HIPMnST1

1. Where n stands for register 1 or 2.

Host Interface PM n Status

Varies per bit

HIPMnDO1

Host Interface PM n Data Out Buffer

HIPMnDOC1

Host Interface PM n Data Out Buffer with SCI

HIPMnDOM1

Host Interface PM n Data Out Buffer with SMI

HIPMnDI1

Host Interface PM n Data In Buffer

HIPMnDIC1

Host Interface PM n Data In Buffer with SCI

HIPMnCTL1

Host Interface PM n Control

R/W

HIPMnIC1

Host Interface PM n Interrupt Control

R/W

HIPMnIE1

Host Interface PM n Interrupt Enable

R/W

Bit

76543210

Name

ST3-ST0

IBF

OBF

Reset

00000000

Bit

Type

Description

0RO

OBF (Output Buffer Full). The bit is set when the PM channel’s DBBOUT is written to by the core

(writing to HIPMnDO, HIPMnDOM or HIPMnDOC register). The bit is cleared by a host processor read

of the output buffer (6216). Writing to this bit is ignored.

1RO

IBF (Input Buffer Full). The bit is set when the PM channel’s DBBIN is written to by the host

processor (writing to either address 6216 or address 6616). The bit is cleared by a core read of the PM

input buffer (HIPMnDI or HIPMnDIC).

R/W

F0 (Flag 0). General-purpose flag that can be set or cleared by the core firmware.

3RO

A2 (A2 Address). Indicates whether the last write operation of the host to the PMn channel was to the

data register or the Command register. Writing to this bit is ignored.

0: Last write was to the data register (pointed to by conﬁguration register index 6016 and 6116)

1: Last write was to the command register (pointed to by conﬁguration register index 6216 and 6316)

7-4

R/W

ST3-ST0 (Status). Four general-purpose ﬂags that can be used for signaling between the host and

core. When used as an embedded controller interface channel for ACPI, a predeﬁned meaning is

assigned to ST0, ST1 and ST2. The standard meaning is BURST, SCI event and SMI event,

respectively.

PC87591L Datasheet(PDF) 291 Page - National Semiconductor (TI)

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