PC87591L datasheet(295/437 Pages) NSC

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5.0 Host Controller Interface Modules (Continued)

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Host Interface PM n Interrupt Control Register (HIPMnIC)

The HIPMnIC register and its bits affect operation in Enhanced mode only (i.e., when EME bit in HIPMnCTL register is set).

In PC87570 Legacy mode, the bits in this registers are ignored. HIPMnIC controls the PM n interrupt signals mode of oper-

ation. HIPMnCTL is 4116 on reset.

Location: Channel 1 - 00 FEBA16

Channel 2 - 00 FECC16

Type: R/W

Bit

76543210

Name

SCIIS

SMIPOL

PLMM

SCIB

SMIB

IRQB

Reset

01000001

Bit

Description

IRQB (Host Interrupt Request Control Bit). When the IRQ signal is conﬁgured for direct control by the

ﬁrmware (HIRQE in HIPMnIE register is 0), IRQB bit is output to the PMnIRQ signal. When read, IRQB bit

returns the current value of the PMnIRQ signal. IRQn signal’s value can be read regardless of the state of

HIRQE in HIPMnIE register.

SMIB (Host SMI Request Control Bit). When the SMI signal is conﬁgured for direct control by the ﬁrmware

(HSMIE in HIPMnIE register is 0), SMIB bit is output to the PMnSMI signal (if SMIPOL=0, SMIB is output; if

SMIPOL=1, SMIB is inverted before output). When read, SMIB bit returns the current value of the SMI pin. The

SMI signal’s value can be read regardless of the state of HSMIE in HIPMnIE register.

SCIB (Host SCI Request Control Bit). When the SCI signal is conﬁgured for direct control by the ﬁrmware

(HSCIE in HIPMnIE register is 0), SMIB bit is output to the PMnSCI signal (if SCIPOL=0, SCIB is output; if

SCIPOL=1, SCIB is inverted before output). When read, SCIB bit returns the current value of the SCI pin. The

ECSCI signal value can be read regardless of the state of HSCIE bit in HIPMnIE register.

5-3

PLMM (Pulse Level Mode SMI). Sets the hardware-controlled SMI signal mode to Level or Pulse and sets the

pulse width.

When PLMM = 0002, the SCI signal functions in Level mode. In this mode, the SMI pulse shaper output value is

low, and a high level is set to issue an interrupt (i.e., the respective OBF is set).

When PLMM

≠ 0, the host interrupts are in Pulse mode. In this mode, the SMI pulse shaper output value is low,

and it toggles high to issue an interrupt (i.e., when the respective output buffer register is written).

The pulse widths are:

Bits

5 4 3

Pulse Width

0 0 0:

Level interrupt

0 0 1:

1-Cycle Pulse

0 1 0:

2-Cycle Pulse

0 1 1:

4-Cycle Pulse

1 0 0:

8-Cycle Pulse

1 0 1:

16-Cycle Pulse

Other:

Reserved

SMIPOL (SMI Negative Polarity).

0: SMI output inactive value is low and its active (asserted) value is high

1: Inverted polarity is used. When SMIPOL is set, the SMI signal is either the inverse of what is stored in SMIB or

the output of the SMI pulse shaper.

This bit affects the SMI signal polarity in both PC87570 Legacy and Enhanced modes

SCIIS (SIC on IBF Start). A write of 1 to this bit starts an SCI interrupt on IBF cleared. A write of 0 to SCIIS is

ignored. When read, this bit always return 0.

PC87591L Datasheet(PDF) 295 Page - National Semiconductor (TI)

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