PC87591L datasheet(297/437 Pages) NSC

297 / 437 page

Host Controller Interface Modules (Continued)

Revision 1.07

297

www.national.com

5.3

SHARED MEMORY AND SECURITY

The PC87591x on-chip flash can be shared by the host and the core. It may also be used by the host for BIOS code storage

or other purposes. The on-chip flash resides in the core domain. In IRE and OBD environments, it is accessible via the core

bus. For host accesses, the flash is mapped to the host memory address space via the host interface, and a bridge is pro-

vided between the host bus and the core bus. The bridge functionality includes:

●

Memory mapping between host domain address space and core domain address space

●

Host bus to core bus transaction bridging

●

Locking mechanism between host and core domains to maintain coherence of on-chip ﬂash contents during updates

●

Read/write protection on host accesses to the on-chip ﬂash

●

Host-accessible control and status registers of on-chip ﬂash

●

Signaling interface for host-core communication associated with memory updates

In addition, the PC87591x supports expansion memory controlled by the core domain’s Bus Interface Unit (BIU). The bridge

also supports host accesses to the expansion memory (including read/write protection on these accesses). These accesses

can occur in IRE, OBD and DEV environments.

In the PC87591S, the Shared Memory and Security module also includes a Random Number Generator (RNG). The output

of the RNG is available to the core.

5.3.1

Host Bus to Core Bus Access Translation

A core bus transaction is generated for each of the following types of host bus transactions:

●

8-bit memory read/write

●

8-bit FWH memory read/write

●

8-bit indirect read/write transactions, using I/O read/write to access the shared ﬂash (see Section 5.3.3 on page 300)

Memory and FWH memory read/write transactions drive Long Wait on the Sync field until the transaction is completed on

the core bus. Section 5.3.3 on page 300 describes the Sync field for indirect memory read/write transactions. Section 5.3.5

on page 301 describes the behavior for restricted accesses.

The host bus transaction is forwarded to the core bus after the following is done:

●

Address is translated

●

The translated address and the access type are veriﬁed to be both:

— In core domain’s base memory or expansion memory spaces

— Unprotected

●

For writes (erase/program): on-chip ﬂash is unlocked (HLOCK bit in SMCCST register is set)

Note that host bus read transactions are translated to read transactions on the core bus, and host bus write transactions are

translated to write transactions on the core bus. Translated reads and writes behave the same as reads and writes by the

core. When the erase bit is set and the on-chip flash is enabled and addressed, the effect of a write is the same as a write

after the page erase bit is set.

5.3.2

Memory Mapping and Host Address Translation

Section 6.1.11 on page 349 describes in detail the host domain addresses for which the core bus generates transactions.

In general, the BIOS memory on the host bus can occupy one of three regions in the memory space (see Table 60 on

page 350).

Address translation between the host and the core domains is performed for host memory and FWH memory transactions.

The 32-bit address received from the host bus is used to decode the different zones, as described in Section 6.1.11 on

page 349. The address is then translated to the core bus address using the following rules:

●

Legacy and Extended Legacy BIOS Range

Handle only when enabled (see Section 6.1.11 on page 349 for the enabling alternatives); otherwise, transactions to

this zone are ignored. The address is converted to a shared memory internal address as follows:

SM_Host_Address[31-0] = {1111 1111 1111 111, Host_Memory_Address[16-0]}

●

User Deﬁned Shared Memory Space

This address range is handled only when enabled (see Section 6.1.11 on page 349 for the enabling alternatives);

otherwise, transactions to this zone are ignored. The address translation depends on the window size deﬁned. When

the window size is 2n bytes, the lower ‘n’ bits are taken from the memory address, and the upper 32

− n bits of the

LPC address are replaced with 1. The address is converted to an internal address as follows:

SM_Host_Address[31-0] = {1111 ... ... 1, Host_Memory_Address[n-0]}

PC87591L Datasheet(PDF) 297 Page - National Semiconductor (TI)

PC87591L Datasheet(HTML) 297 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL