PC87591L datasheet(296/437 Pages) NSC

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5.0 Host Controller Interface Modules (Continued)

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Revision 1.07

Host Interface PM n Interrupt Enable Register (HIPMnIE)

The HIPMnIE register controls the PM n interrupt signals that enable SMI, SCI and IRQ interrupts. HIPMnIE is cleared on reset.

Location: Channel 1 - 00 FEBC16

Channel 2 - 00 FECE16

Type: R/W

Bit

76543210

Name

Reserved

HSMIE

HSCIE

HIRQE

SMIE

SCIE

IRQE

Reset

00000000

Bit

Description

IRQE (IRQ Enable).

0: PMnIRQ signal assumes its default value (low) and no interrupts are issued

1: Enables PM generation of IRQ events

SCIE (SCI Enable).

0: PMnSCI signal assumes its default value (high) and no interrupts are issued

1: Enables PM generation of SCI events

SMIE (SMI Enable).

0: PMnSMI signal assumes its default value (high) and no interrupts are issued

1: Enables the generation of SMI events by this module

HIRQE (Hardware IRQ Enable). Works only in Enhanced PM mode.

0: IRQB bit of HIPMnIC register controls the value of the IRQ

1: Enables the generation of IRQ events by hardware control based on the status of the OBF flag

HSCIE (Hardware SCI Enable). Works only in Enhanced PM mode.

0: SCIB bit in HIPMnIC register controls the value of the SCI

1: Enables the generation of SCI events by hardware control based on the status of the OBF and IBF flags

HSMIE (Hardware SMI Enable). Works only in Enhanced PM mode.

0: SMIB bit in HIPMnIC register controls the value of the SMI

1: Enables the generation of SMI events by hardware control based on the status of the OBF flag

7-6

Reserved.

PC87591L Datasheet(PDF) 296 Page - National Semiconductor (TI)

PC87591L Datasheet(HTML) 296 Page - National Semiconductor (TI)

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