PC87591L datasheet(294/437 Pages) NSC

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5.0 Host Controller Interface Modules (Continued)

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Revision 1.07

Host Interface PM n Control Register (HIPMnCTL)

The HIPMnCTL register controls the operation mode and configuration of the PM channel. It includes the Enhanced mode

enable bit and control bits for Enhanced mode operation. HIPMnCTL is 4016 on reset.

Location: Channel 1 - 00 FEB816

Channel 2 - 00 FECA16

Type: R/W

Bit

76543210

Name

EME

SCIPOL

PLMS

Reserved

OBEIE

IBFIE

Reset

see text

1000000

Bit

Description

IBFIE (Input Buffer Full Interrupt Enabler).

0: IBF interrupt to the core is disabled

1: Enables an interrupt to the core when IBF in HIPMnST register is set

OBEIE (Output Buffer Empty Interrupt Enable).

0: OBF interrupt to the core is disabled

1: Enables an interrupt to the core when OBF in HIPMnST register is set

Reserved.

5-3

PLMS (Pulse Level Mode SCI). Sets the hardware-controlled SCI signal mode to be Level or Pulse and sets

the pulse width.

When PLMS = 0002, the SCI signal functions in Level mode. In this mode, the SCI pulse shaper output value is

low, and a high level is set to issue an interrupt (the respective OBF is set).

When PLMS

≠ 0, the host interrupts are in Pulse mode. In this mode, the SCI pulse shaper output value is low,

and it toggles high to issue an interrupt (i.e., when the respective output buffer register is written).

The pulse widths are:

Bits

5 4 3

Pulse Width

0 0 0:

Level interrupt

0 0 1:

1-Cycle Pulse

0 1 0:

2-Cycle Pulse

0 1 1:

4-Cycle Pulse

1 0 0:

8-Cycle Pulse

1 0 1:

16-Cycle Pulse

Other:

Reserved

SCIPOL (SCI Negative Polarity).

0: SCI output inactive value is low and its active (asserted) value is high

1: Inverted polarity is used. When SCIPOL is set, the SCI signal is the inverse of either what is stored in SCIB or

the output of the SCI pulse shaper.

This bit affects the SCI signal polarity in both PC87570 Legacy and Enhanced modes.

EME (Enhanced Mode Enable).

0: PM channel is used in Legacy mode. HIPMnST status bits are controlled by writes to the bit value, and inter-

rupts are controlled by HICTRL and HIIRQC register bits (default for HIPM1CTL).

1: Enables enhanced control of the PM channel. The bits in HICTRL and HIIRQC registers are ignored in this case

(default for HIPM2CTL).

In HIPM2CTL (i.e., for PM channel 2), EME is a read-only bit that holds the value 1. Writes to this bit are

ignored.

PC87591L Datasheet(PDF) 294 Page - National Semiconductor (TI)

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