PC87591L datasheet(298/437 Pages) NSC

298 / 437 page

Host Controller Interface Modules (Continued)

www.national.com

298

Revision 1.07

●

386 Mode-Compatible BIOS Range and User Deﬁned Shared Memory Range

This address range is handled only when enabled (see Section 6.1.11 on page 349 for the enabling alternatives);

otherwise, transactions to this zone are ignored. The address is converted to an internal address as follows:

SM_Host_Address[31-0] = Host_Memory_Address[31-0]

●

Indirect Memory Address

This address speciﬁed in IMA3-0 is used as follows:

SM_Host_Address[31-0] = {IMA3[7-0], IMA2[7-0], IMA1[7-0], IMA0[7-0]}

●

For allowed addresses, the SM_Host_Address is translated to a core address using the following equation

(a 21-bit address in the core address space is generated by adding the host memory address to the MBTA):

CR_Space_Address[20-0] = (21 least signiﬁcant bits)(SM_Host_Address + MBTA)

MBTA is the size of the PC87591x on-chip flash memory, as defined in the Shared Memory Main Block Top Address

may be changed to allow code development for other flash sizes.

●

The CR_Space_Address[21-0] is checked against the Host-Controlled Access Protection registers, the Core-Con-

trolled Override Protection registers and general address space access limitations (i.e., space not mapped to the

base memory or expansion memory).

Figure 99 illustrates the address translation scheme for shared memory transactions.

Access restrictions are based on the contents of the host-controlled and core-controlled access protection registers. The

access protection logic may prevent read and/or write access to addresses in the core address space. The core-controlled

register setting should always prevent host access to addresses that are not in the core domain’s base memory or expansion

memory spaces. Note that the resulting memory space is not continuous.

In DEV environment, the value of MBTA may be changed for ease of software development. The memory space between

MBTA (1 000016 in PC87591E or 2 000016 in PC87591S) to F FFFF16 is not accessible by the host.

The following figures illustrate the mapping function that results from the address translation function for a Shared BIOS

scheme (Figure 100) and when the flash is mapped as a non-BIOS block of memory (Figure 101).

FWH ID Check

Address

Translation

LPC

Bus

Transaction Type &

Memory Address

Decoders

0-16

17-31

“1”

Legacy & Extended

BIOS Range

Memory R/W

Address

MBTA

Indirect Memory Access

Reset or

IMA0-3

Core Write

Access

Protection

Logic

Access

Protection

Registers

Override

Protection

Registers

0-20

0-31

Core Bus

Address

Host-Controlled

Core-Controlled

Figure 99. Address Translation Mechanism for 512 Kbyte On-Chip Flash

MBTA

0-20

SM_Host_Address

386 BIOS Range

0-31

0-(win_size_bits

− 1)

win_size_bits

− 31

“1”

User Def. Space

PC87591L Datasheet(PDF) 298 Page - National Semiconductor (TI)

PC87591L Datasheet(HTML) 298 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL