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PC87591L Datasheet(PDF) 302 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # PC87591L
Description  LPC Mobile Embedded Controllers
PDF  437 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC87591L Datasheet(HTML) 302 Page - National Semiconductor (TI)

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Host Controller Interface Modules (Continued)
www.national.com
302
Revision 1.07
The block number may be calculated using the following equation:
Core_Block_Number = (CR_Space_Address < 128K) ?
CR_Space_Address[20-0] / 64K : CR_Space_Address[20-0] / 8K
The Shared Memory Core Override Read Protect 0-2 registers and Shared Memory Core Override Write Protect 0-2 regis-
ters provide core access to the read and write protect bits, respectively. Bits in these registers may be set and cleared by
writing to the registers.
Response to a Restricted Access
A restricted access is an access that complies with at least one of the following conditions:
●
The access type (i.e., Read or Write) of the translated host address (i.e., core address) is protected.
●
A reset to the core domain due to a Warm reset event or a flash empty indication is set (Core Boot Block field of the
protection word is 11112).
The PC87591x responds to a restricted access by generating an interrupt (if enabled by HERRIEN bit in SMCCST register)
to the core. Two status bits (HWERR and HRERR) indicate whether the restricted access is a read or write access. The
response on the host bus is according to the HERES field.
For restricted write accesses: Data written is ignored; when the HERES field is 102, the read or write transaction is completed
with an error SYNC; otherwise, it is completed with a ready SYNC.
For restricted read accesses: When the HERES field is 002, the read or write transaction drives Long Wait (endlessly, unless the
access becomes unrestricted or the HERES field is changed). When the field is 012, the PC87591x completes the transaction
with a ready SYNC and data of 0016; when the field is 102, it completes the transaction with an error SYNC and data of 0016.
Figure 102. Protection Blocks for Protection Bits and Override Protection Bits
Area Not Accessible
to Host
00 0000
01 0000
02 0000
03 0000
0F 0000
10 0000
11 0000
12 0000
1F 0000
1F FFFF
~
~
~
~
~
~
~
~
Address in
Core Address
Space
8K
8K
8K
8K
8K
8K
8K
64K
64K
64K
64K
64K
64K
64K
04 0000
00 E000
64K
Host Block
Index
Core Override
LA 0
LA 1
LA 2
LA 6
LA 8
LA 15
2
3
15
16
17
31
2
3
15
16
17
31
1
0
MBTA
Block Number



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