PC87591L datasheet(301/437 Pages) NSC

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The core can clear HLOCK bit at any time, preventing any further erase or program operations by the host.

5.3.5

Host Access Protection

The host read/write protection is software controlled via a set of registers accessible to the host. The protection granularity

is per block. Each of the 32 software-controlled protection blocks is 64 Kbytes; the block’s read protection and write protec-

tion flags may be set independently. A Lock Protect flag may be set to prevent future changes to the read and write protection

bits. Once locked, the lock bit and the read/write enable bits may be changed only after Host Domain Hardware reset.

The core can override the host settings and prevent host access to certain areas of the shared memory. The override may

be set independently for read and write. In the first 128 Kbytes of address space, each core-controlled block is 8 Kbytes. For

the rest of the memory space the blocks are 64 Kbytes each.

The default value of the protection registers is set according to the properties of the block. There are three types of blocks:

●

Core Boot Block:Read, Erase and Program protected from the host.

●

Host Boot Block:Open for Read by the host; Erase and Program protected from the host.

●

Other Blocks:Open for Read, Erase and Program by the host.

Core on-chip peripherals and RAM are never accessible to the host (for both read and write). The range from MBTA to

0 FFFF16 should be protected from host access using the core-controlled protection registers.

The size of any of the above blocks is defined as part of the flash protection information. This information is stored in the

flash information block at address FE16. This information is updated while the flash is programed or during a Special Erase,

through either the JTAG or Parallel Interface.See Section 4.16.6 on page 226 for information about protection information

fields.

Core Boot Block

This block is not accessible by the host and (for either read nor write). The core boot block starts at address 0 000016 and

ends as defined in the protection information field (8 Kbytes to 128 Kbytes in steps of 8 Kbytes). The core boot block access

protection settings may not be changed, and the respective protection bits are read only.

Host Boot Block

By default, this block may be read by the host. Host writes to this block are always disabled. The host boot block size is

64 Kbytes and is available when the Host Boot Block bit in the protection word is cleared. The Host boot block is always the

last 64 Kbytes of the base memory (i.e., MBTA

− 64 Kbytes to MBTA − 1 Kbyte). In case of an overlap between the host

boot block and the core boot block, access protection settings of the core boot block are used. The host boot block access

protection settings may not be changed, and the respective protection bits are read only.

Other Blocks

By default, all other blocks are read and write protected. The core may enable host read and/or write access to these blocks.

Setting the Host Access Protection Flags

There are two sets of host access protection flags, as shown in Figure 102:

●

Host-controlled host access protection ﬂags

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Core-controlled host access protection ﬂags

Host-Controlled Host Access Protection Flags. For each of the 32 protection blocks there is a set of three bits (flags):

Read Protect, Write Protect and Lock Protect. The 32 sets of flags are accessible via two registers, Shared Memory Host

Access Protect Register 1 and 2 (SMHAP1-2), using an indexing scheme.

The Host Block index may be calculated using the following equation:

Host_Block_Index = CR_Space_Address[20-0] / 64K or

Host_Block_Index = (21 least signiﬁcant bits)(SM_Host_Address + MBTA) / 64K

See Section 5.3.2 on page 297 for the definitions of the host address translation.

●

To change a ﬂag setting, write the new ﬂag setting, together with the required index ﬁeld (i.e., Host Access Protection

Index) and a cleared Index Write bit, to the appropriate register (SMHAP1 or SMHAP2).

●

To read the values of the ﬂags:

1. Read the value of the register and save the index ﬁeld.

2. Write the index of the register’s ﬂag (i.e., write the index with a 1 in the Index Write bit).

3. Read the settings of the register’s ﬂag.

4. Restore the index ﬁeld by writing back the value of the index ﬁeld stored in step 1.

Core-Controlled Access Protection Flags. For core-controlled host access protection there is a read protect and write pro-

tect bit for each block The core block number are parallel to the host blocks for blocks 2-31. The core-controlled host access

protection has a finer granularity for the first two host blocks, which are split into 16 core blocks, indicated as LA0 - LA15.

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