PC87591L datasheet(306/437 Pages) NSC

306 / 437 page

Host Controller Interface Modules (Continued)

www.national.com

306

Revision 1.07

Shared Memory Host Access Protect Register 1 and 2 (SMHAP1-2)

This register holds the read/write protection and lock control from the host side to the shared memory. The memory is par-

titioned into 64 Kbyte blocks. SMHAP1 controls the first 16 blocks (addresses 0-1 Mbyte). SMHAP2 controls the second

group of 16 blocks (addresses 1-2 Mbyte). The block mapping is in the core address space. See “Setting the Host Access

Protection Flags” on page 301 for the calculation method of the block address in the host address space. On Host Domain

Hardware reset, all write-protect flags are set and all lock-protect and read-protect flags are cleared.

Location: Offset 0716 and 0816

Type: Varies per bit

Shared Memory Host Semaphore Register (SMHSEM)

This register provides eight semaphore bits between the core and host. Four of the bits may be set by the host and four may

be set by the core. The register is cleared (0016) on Host Domain Hardware reset.

Location: Offset 0C16

Type: Varies per bit

R/W1C HDERR (Host Data Loss Error). The bit is set (1) when a write to a full buffer is detected. The bit is

cleared by writing 1 to it.

This bit can be cleared only when HBUSY bit is cleared (0).

7-5

Reserved.

Bit

765

3210

Name

Host Access Protection Index

Index Write

Host Lock

Protection

Host Write

Protection

Host Read

Protection

Reset

Bit

Type

Description

R/W

Host Read Protection. The block number is as held in the index field (bits 7-4). Note that the Core

Override protection may disable reads even when reads are allowed by this register.

0: Host Reads are allowed for this block

1: Host Reads are inhibited for this block

R/W

Host Write Protection. The block number is as held in the index field (bits 7-4). Note that the Core

Override protection may disable writes even when writes are allowed by this register.

0: Program and erase are allowed for this block

1: Program and erase are inhibited for this block

R/W

Host Lock Protection. The block number is as held in the index field (bits 7-4). When set, the bit

prevents changing the values of the Host Read Protect, Host Write Protect and Host Lock Protection

bits for this block. Once set, this bit is cleared by Host Domain Hardware reset only.

0: Changes to protection bits (0-2) for this block are enabled

1: Protection bits (0-2) for this block are locked, and the bits’ values may not be changed

3WO

Index Write. Indicates that this is an index write transaction; therefore, bits 0-2 of this register are

ignored. When read, always returns 0.

0: Write transaction affects all fields of this register (writes to bits 0-2 use the newly written index)

1: Write transaction for purpose of index update; bits 0-2 should not be updated by this write.

7-4

R/W

Host Access Protection Index. Holds the index number of the host block accessed by the other fields

in this register. All blocks are 64 Kbytes. The block index is calculated in the core address space. For

details of the address conversion, see Section 5.3.2 on page 297.

Index = Block_First_Address / 64K

In SMHAP1: 0000-111116 for indexes 0-15, respectively

In SMHAP2: 0000-111116 for indexes 16-31, respectively

Bit

Type

Description

PC87591L Datasheet(PDF) 306 Page - National Semiconductor (TI)

PC87591L Datasheet(HTML) 306 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL