PC87591L datasheet(308/437 Pages) NSC

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Host Controller Interface Modules (Continued)

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Shared Memory Core Top Address Register (SMCTA)

This register provides information about the size of the on-chip main block. The register is loaded with its default value on

VCC Power-Up reset only.

Location: 00 F90216

Type: RO in IRE and OBD environments

R/W in DEV environment

Shared Memory Host Semaphore Register (SMHSEM)

This register provides eight semaphore bits between the core and the host. Four of the bits may be set by the host; four may

be set by the core. The register is cleared (0016) on reset.

Location: 00 F90416

Type: Varies per bit

4-3

HERES (Host Error Response). Controls response type on read/write from/to a protected block or out-of-range

address. An out-of-range address is an address that the LPC conﬁguration module deﬁnes as mapped to the

PC87591x, but it is actually translated to a reserved address in the core address space.

Bits

4 3

Description

0 0:

Drive Long Wait for read; ignore write

0 1:

Read back 0016; ignore write

1 0:

Drive error SYNC for both read and write

1 1:

Reserved

HLOCK (Host Lock).

0: The bridge does not generate write transactions on the core bus

1: The bridge can generate write transactions on the core bus

This bit should be set only when FMBUSY bit is cleared (see ”Flash Memory Status Register (FLSR)” in

Section 4.16.7 on page 228).

HSEMW (Host Semaphore Write). The bit is set (1) when the host writes to HSEM register. Writing 1 to this

bit position clears it to 0. Writing 0 has no effect.

HSEMIE (Host Semaphore Interrupt Enable). When the bit is set (1), the interrupt to the core is set (level

high) if HSEMW is set.

Bit

76543

Name

Reserved

MBSD

Reset

2 (see note in ﬁeld description)

Bit

Description

4-0

MBSD (Main Block Size Deﬁnition). Defines the size of the main block in 64 Kbyte units. Thus the MBTA value

is MBSD * 1 000016. Note that MBTA is actually the ﬁrst address beyond the main block.

The reset value of this ﬁeld is affected by the Force MBTA Zero bit in the protection word (see Section 4.16.6 on

page 226). When the Force MBTA Zero bit is set, the reset value of this ﬁeld is 016; when the bit is cleared, the

reset value is as shown in the bit table, above.

This ﬁeld is loaded on VCC Power-Up reset with the on-chip ﬂash size. In DEV environment, the MBSD may be

loaded with a new value.

7-5

Reserved.

Bit

76543

Name

CSEM3

CSEM2

CSEM1

CSEM0

HSEM3

HSEM2

HSEM1

Reset

Bit

Description

PC87591L Datasheet(PDF) 308 Page - National Semiconductor (TI)

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