PC87591L datasheet(307/437 Pages) NSC

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Host Controller Interface Modules (Continued)

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5.3.9

Shared Memory Core Registers

The following set of registers is accessible only by the core. These registers are maintained by VCC.

For a summary of the abbreviations used for Register Type, see Section 2 on page 34.

Shared Memory Core Register Map

Shared Memory Core Control and Status Register (SMCCST)

This register provides control and status of read/write from/to a restricted address. The register is cleared (0016) on reset.

Location: 00 F90016

Type: R/W

Bit

76543

Name

CSEM3

CSEM2

CSEM1

CSEM0

HSEM3

HSEM2

HSEM1

HSEM0

Reset

Bit

Type

Description

3-0

R/W HSEM3-0. Four bits that may be updated by the host and read by both the host and the core.

7-4

CSEM3-0. Four bits that may be updated by the core and read by both the host and the core.

Mnemonic

Type

SMCCST

Shared Memory Core Control and Status

R/W

SMCTA

Shared Memory Core Top Address

RO in IRE and OBD environments;

R/W in DEV environment

SMHSEM

Shared Memory Host Semaphores

Varies per bit

SMCORP0-2

Shared Memory Core Override Read Protect 0-2

R/W or RO

SMCOWP0-2

Shared Memory Core Override Write Protect 0-2

R/W or RO

RNGCS

Random Number Generator Control and Status

Varies per bit

RNGD

Random Number Generator Data

Bit

76543

Name

HSEMIE

HSEMW

HLOCK

HERES

HERRIEN

HWERR

HRERR

Reset

0000

Bit

Description

HRERR (Host Read Error). The bit is set (1) when the host attempts to read from a read-protected block or

out-of-range address. An out-of-range address is an address that the LPC conﬁguration module deﬁnes as

mapped to the PC87591x, but it is actually translated to a reserved address in the core address space. Writing

1 to this bit clears it to 0. Writing 0 has no effect.

HWERR (Host Write Error). The bit is set (1) when the host attempts to write to a read-protected block or out-

of-range address. An out-of-range address is an address that the LPC conﬁguration module deﬁnes as mapped

to the PC87591x, but it is actually translated to a reserved address in the core address space. Writing 1 to this

bit clears it to 0. Writing 0 has no effect.

HERRIEN (Host Error Interrupt Enable). When set (1) and either the HRERR or HWERR bit is set (1), a core

interrupt is generated; otherwise, the core interrupt is inactive.

PC87591L Datasheet(PDF) 307 Page - National Semiconductor (TI)

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