PC87591L datasheet(309/437 Pages) NSC

309 / 437 page

Host Controller Interface Modules (Continued)

Revision 1.07

309

www.national.com

Shared Memory Core Override Read Protect Registers 0-2 (SMCORP0-2)

SMCORP0-2 are 16-bit registers that provide core override on the host read protection bits. For the host to be able to read

a memory location, both the Host Read Protection bit (controlled through the Shared Memory Host Access Protect Register

1 or 2) and the associated bit in SMCORP0-2 should be cleared. Each bit in this register is associated with a memory block,

as described in the bits description. Bits in these registers may be RO or RW depending on their position and the size of the

core and host boot blocks. SMCORP0-2 registers are loaded with reset values either on reset or when the value of the

SMCTA register is changed; the reset values depend on the size of the core and host boot blocks, as defined in the protec-

tion word.

Location: 00 F91016, 00 F91216, 00 F91416

Type: R/W or RO as described in the description below

Bit

Type

Description

3-0

HSEM3-0. Four bits that may be updated by the host and read by both the host and the core.

7-4

R/W CSEM3-0. Four bits that may be updated by the core and read by both the host and the core.

Bit

9876

43210

Name

ORPLA15-0

Reset

See bit description below

Bit

9876

43210

Name

ORP15-2

Reserved

Reset

See bit description below

Bit

9876

43210

Name

ORP 31-16

Reset

See bit description below

Bit

Description

15-0 ORPLA15-0 (Override Read Protect Low Addresses 15 through 0).

ORP15-2 (Override Read Protect 15 through 2).

ORP31-16 (Override Read Protect 15 through 0).

Each bit affects the host’s ability to read from one block. On the low addresses (covered by ORPLAi), the block

size is 8 Kbytes. For the other blocks it is 64 Kbytes. The block address is calculated as follows:

Low address blocks, ORPLAi: from i*8K to (i+1)*8K

−1

Other blocks, ORPLj: from j*64K to (j+1)*64K

See Figure 102 on page 302 for a description of the block mapping. Bit 7 (ORPLA7) in SMCORP0 register is

read only.

0: Do not override the host read protect setting for the block

1: Host read for this block is disabled regardless of the setting of the respective bit in the host register

The reset values of these registers are as follows:

Core boot blocks that cover address 00 000016 to CR_Boot_Block_Size:

Host boot blocks not in above group and from (MBTA1

− Host_Boot_Block_Size) to MBTA:

All other blocks:

The following access limitations apply to the register bits:

Core boot blocks that cover address 00 000016 to CR_Boot_Block_Size:

Host boot blocks not in above group and ranging from (MBTA1

− Host_Boot_Block_Size) to MBTA:RO

All other blocks:

1. Use the MBTA as speciﬁed in SMCTA register, without the MBTA override in the protection word.

PC87591L Datasheet(PDF) 309 Page - National Semiconductor (TI)

PC87591L Datasheet(HTML) 309 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL