PC87591L datasheet(312/437 Pages) NSC

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Host Controller Interface Modules (Continued)

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Revision 1.07

Random Number Generator Data Register, RNGD (PC87591S)

This register provides the random number value of the RNG.

Location: 00 F93216

Type: RO

5.3.10 Usage Hints

●

After clearing (0) HLOCK bit, the core ﬁrmware should wait until FMBUSY bit is clear (0) before it accesses the on-

chip ﬂash (see ”Flash Memory Status Register (FLSR)” in Section 4.16.7 on page 228).

●

Enable Access to the shared memory: Before any access may occur, the shared memory access must be enabled

using the SIO Conﬁguration registers (see Section 6.1.11 on page 349). To enable shared memory as a boot device,

the SHBM strap should be set appropriately (see Section 2.2.11 on page 50).

●

Host boot block may be implemented as part of the on-chip ﬂash or in the external memory. In the latter case, access

to the Host boot block must be enabled by the core after the memory access conﬁguration is completed.

●

For host shared memory read:

1. Have host enable the memory for reading (if disabled), using SMHAP1 and SMHAP2 registers.

2. Have core enable the memory for reading (in most cases, disabled by default), using SMCORP0-2 registers.

3. Read from the designated address location.

●

For host shared memory write or erase:

1. Have host enable the desired location for write, using SMHAP1 and SMHAP2 registers (note that the memory

may be disabled for reads if the hardware validation is in use).

2. Have core enable the desired location for a write, using SMCOWP0-2 registers.

3. Enable the host write operations by setting HLOCK bit in SMCCST register.

4. To perform a page erase operation, the host should set PMER bit in SMHC register and write any data to

an address in the page. The page is erased when HBUSY bit in SMHST register is cleared, and an erase

error, if it occurs, is ﬂagged by HEERR bit in SMHST register.

5. To program a byte in the on-chip ﬂash, the host should make sure PMER bit in SMHC register is clear

and write the required data to the designated address location. The programing is completed when HBUSY bit

in SMHST register is cleared. At this time, an erase error, if it occurs, is ﬂagged by HPERR in SMHST register.

6. Programing the expansion memory is done using read/write operations to addresses associated with that memory.

The transactions are passed to the memory through the core bus and BIU modules. The software should perform

the appropriate sequence of read and write operations as required by the ﬂash device in use.

●

At different stages of the ﬂash programing by the host, communication between the core and host is required. Various

mechanisms may be used for this, one of which is the Shared Memory Semaphore mechanism. This mechanism is

tuned for host-initiated operations that use polling on the registers. The core may receive an interrupt or use polling

to identify a semaphore change. An example of bit allocation is:

Bit 0 - Host requests control of ﬂash

Bit 4 - Core grants control to host

The sequence is:

1. Host sets bit 0 to request control of bus.

2. Core identiﬁes that bit 0 is set and does the required operations, including setting HLOCK bit in

SMCCST register to enable host access.

3. Core sets bit 4, indicating to the host that memory access is granted.

4. Host performs write/erase to the memory, as required.

5. Host clears bit 0, indicating completion of the process.

6. Core clears HLOCK and protects the memory.

7. Core indicates completion of process by clearing bit 4.

Bit

76543

Name

RNGD7-0

Bit

Description

7-0

RNGD0-7 (Random Number Generator Data Bits). Provides random data output from the RNG module. When

DVALID in RNGCS register is cleared, RNGD register always reads 0016. When DVALID in RNGCS register is

set, the data read is a random number. Any random number can be read only once, after which it is marked as

invalid and replaced by a new number.

PC87591L Datasheet(PDF) 312 Page - National Semiconductor (TI)

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