PC87591L datasheet(311/437 Pages) NSC

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Host Controller Interface Modules (Continued)

Revision 1.07

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Random Number Generator Control/Status Register, RNGCS (PC87591S)

This register controls the Random Number Generator (RNG) unit. It also provides status of its operation and the validity of

the numbers at its output. The register is cleared on reset.

Location: 00 F93016

Type: Varies per bit

Bit

76543

Name

Reserved

CLKP

DVALID

RNGE

Reset

0000

Bit

Type

Description

R/W

RNGE (Random Number Generator Enable). Enables the operation of the RNG. This bit should be

cleared to reduce power consumption when the RNG is not required. Some wake-up time may apply

before the ﬁrst number is generated after RNG activation.

0: RNG disabled (default)

1: RNG enabled

1RO

DVALID (Data Valid). Indicates that valid data may be read from RNGD register.

0: Data not valid; RNGD always reads 0016 (default)

1: Data valid; a random number is read

4-2

R/W

CLKP (Clock Pre-Scaler). Defines the pre-scale ratio between the RNG internal clocks and the core

clock. To change the CLP contents: (a) Clear RNGE; (b) Change CLKP (c); Set RNGE to re-enable the

RNG. CLKP may be set to a value above the actual clock frequency of the core, but it should not be

set to a lower value than the CLK frequency.

Bits

4 3 2

Description

0 0 0:

15-20 MHz (default)

0 0 1:

12-15 MHz

0 1 0:

9-12 MHz

0 1 1:

7-9 MHz

1 0 0:

6-7 MHz

1 0 1:

5-6 MHz

1 1 0:

4-5 MHz

1 1 1:

3-4 MHz

7-5

Reserved.

PC87591L Datasheet(PDF) 311 Page - National Semiconductor (TI)

PC87591L Datasheet(HTML) 311 Page - National Semiconductor (TI)

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