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PC87591L Datasheet(PDF) 292 Page - National Semiconductor (TI) |
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PC87591L Datasheet(HTML) 292 Page - National Semiconductor (TI) |
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292 / 437 page ![]() 5.0 Host Controller Interface Modules (Continued) www.national.com 292 Revision 1.07 Host Interface PM n Data Out Buffer (HIPMnDO) The HIPMnDO register allows the core firmware to write to the PM port DBBOUT register while setting the PM port OBF bit in the Status register. If enabled, an IRQ11 (and/or SCI and/or SMI, in PC87570 Compatible mode) interrupt is sent at that time. If the core interrupt on PM port output buffer empty is enabled, writing to HIPMnDO de-asserts it (low). If DMA on output buffer empty is enabled, the DMA request is de-asserted on the write to HIPMnDO. Location: Channel 1 - 00 FEAE16 Channel 2 - 00 FEC016 Type: WO Host Interface PM n Data Out Buffer with SCI (HIPMnDOC) The HIPMnDOC register has the same function as the HIPMnDO register. In addition, it generates an SCI interrupt when OBF is set and hardware SCI generation is enabled. Location: Channel 1 - 00 FEB216 Channel 2 - 00 FEC416 Type: WO Host Interface PM n Data Out Buffer with SMI (HIPMnDOM) The HIPMnDOM register has the same function as the HIPMnDO register. In addition, it generates an SMI interrupt when OBF is set and hardware SMI generation is enabled. Location: Channel 1 - 00 FEB416 Channel 2 - 00 FEC616 Type: WO Bit 76543210 Name PM Channel DBBOUT Data Bit Description 7-0 PM Channel DBBOUT Data. Bit 76543210 Name PM Channel DBBOUT Data Bit Description 7-0 PM Channel DBBOUT Data. Bit 76543210 Name PM Channel DBBOUT Data Bit Description 7-0 PM Channel DBBOUT Data. |
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