PC87591L datasheet(289/437 Pages) NSC

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5.0 Host Controller Interface Modules (Continued)

Revision 1.07

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When data is written to HIPMnDOM register, the OBF flag and the internal OBF_SMI flag are set and an SMI interrupt is

generated. The OBF_SMI flag is cleared when OBF flag is cleared. The SMI is generated as a pulse whose width is defined

by PLMM in HPIMnIC register.

The SMI interrupt is routed to the SMI pin only if both HSMIE and SMIE bits in HIPMnIE register are set. When SMIE is set

and HSMIE is cleared, SMIB in HIPMnIC register is used as the PMnSMI signal value. When SMIE is cleared, the PMnSMI

signal is inactive (high).

When data is written to HIPMnDOC register, the OBF flag and OBF_SCI internal flag are set and an SCI interrupt is gener-

ated. OBF_SCI is cleared when OBF is cleared. The SCI is generated as a pulse whose width is defined by PLMS in

HPIMnCTL register.

When data is read from HIPMnDIC register, the IBF flag is cleared, the IBF_SCI Internal flag is set and an SCI interrupt is

generated. The IBF_SCI flag is cleared when the IBF is set again. The SCI is generated as a pulse whose width is defined

by PLMS in HPIMnCTL register. Reading from HIPnDI register clears the IBF flag but does not generate an SCI interrupt.

Note that IBF_SCI flag may also be set by writing a 1 to SCIIS bit in HIPMnIC register. This is done to start an SCI interrupt

on input buffer empty without a read operation from the input buffer.

The SCI interrupt is routed to the SCI pin only if HSCIE and SCIE in HIPMnIE register are set. When SCIE is set and HSCIE

is cleared, the value of SCIB in HIPMnIC register is used as the PMnSCI signal value. When SCIE is cleared, PMnSCI is

inactive (high).

Status Read

The status of the PM channel data buffers can be read by both the host and the core. Bits 2 and 4-7 can be written by the core.

The host processor should read the Status register I/O address (legacy 6616, for channel 1) to obtain the contents of the Status

register. The core software should read/write the HIPMnST register to access the same information. The format of the Status

Hardware

IRQM field (HIIRQC)

Interrupt

IRQNPOL bit (HIIRQC)

IRQB bit (HIPMnIC)

(Part of

Module)

IRQ

and

IRQE bit (HIPMnIE)

SMIE bit (HIPMnIE)

Gathering

SMI

OBF bit

SuperI/O

Config

Routing

Polarity

IRQ

Serializer

IRQB bit (HIPMnIC)

HIPMnDOM (write)

HIPMnDI (read)

HIPMnDO (write)

HIPMnDIC (read)

set OBF_no_int

set OBF_SMI

HIPMnDOC (write)

set OBF_SCI

clear IBF bit (HIPMnST)

SMIB bit (HIPMnIC)

SCIB bit (HIPMnIC)

Pulse Shape

Figure 98. IRQ, SCI and SMI Control, Enhanced PM Mode

PLMM field (HIPMnIC)

PLMS field (HIPMnCTL)

HSMIE bit (HIPMnIE)

HSCIE bit (HIPMnIE)

HIRQE bit (HIPMnIE)

PMnSMI

Pulse Shape

Source

ECSCI

set IBF_SCI

SCIIS bit (HPMnIC)

(write 1)

SMIPOL bit (HIPMnIC)

SCIPOL bit (HIPMnCTL)

SCIE bit

PMnECSCI of

other channel

PMnECSCI

SCIB bit (HIPMnIC) (read)

SMIB bit (HIPMnIC)

(write)

(read)

(HIPMnIE)

(HIPMnST)

(read)

PC87591L Datasheet(PDF) 289 Page - National Semiconductor (TI)

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