PC87591L datasheet(322/437 Pages) NSC

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Host Controller Interface Modules (Continued)

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Revision 1.07

5.5.4

Other MSWC Controlled Elements

In addition to its Power Management functions, the MSWC controls the handling of the following system control elements:

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Host Conﬁguration Address Selection

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Host Keyboard Reset Fast Reset Output (KBRST)

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GA20 Pin Functionality

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Host Power on indication

Host Conﬁguration Address Selection

The standard strap configuration enables the selection of one of two SuperI/O configuration register addresses. When the

PC87591x is enabled in Programmable Configuration Address mode (see Table 47 on page 335), the core may set the ad-

dress of the SuperI/O configuration index/data registers.

HCFGBAL and HCFGBAH are byte-wide read/write registers. HCFGBAL holds the least significant byte of a host mother-

board PnP initial configuration address; HCFGBAH holds the most significant byte. The contents of HCFGBAH and HCFG-

BAL change only during VCC Power-Up reset.

To update the base address of the SuperI/O configuration index/data registers, do the following:

1. Clear VHCFGA bit in MSWCTL1 register by writing 1 to it.

2. Write the lower byte of the address to HCFGBAL (MSB must be cleared).

3. Write the higher byte of the address to HCFGBAH.

4. Set HCFGLK bit to prevent an accidental change of the address written to HCFGBAL and HCFGBAH.

The base address is preserved by VCC, and VHCFGA is set as long as a valid address is maintained. If there is no valid

configuration base address, the LPC interface does not respond to configuration requests.

Host Keyboard Fast Reset

The Host Keyboard Reset output (KBRST) is an output of the PC87591x that serves as one of the sources for Host Soft

reset commands (i.e., INIT input in the x86 processors). Figure 107 shows the KBRST generation scheme. The host is reset

when the KBRST output is low. A reset command is issued by the PC87591x by software or hardware, as follows:

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Software: The core ﬁrmware can issue a reset command to the host by writing 1 to HRSTOB in MSWCTL1 register.

The reset to the host ends by writing 0 to this bit.

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Hardware: The host is reset during VCC Power-Up reset if HRAPU bit in MSWCTL3 register is set and an LPC trans-

action is started. This is used to prevent accesses to the PC87591x from being ignored due to the duration of the

Power-Up reset.

GA20 Pin Functionality

The GA20 (Gate Address A20) function is part of the PC architecture. In PC87591x, the GA20 function is implemented by a

GPIO signal that is configured as output. Port PB5 is recommended to be used as GA20 since its default state after reset is

output driving high. The firmware running on the core may change the GA20 signal state by modifying bit 5 in PBDOUT reg-

ister. There is no special hardware or multiplexing on PB5; since there is no multiplexing, bit 5 of PBALT register is always

0 and any writes to it are disregarded. PB5 may be used as a GPIO; however, note that wake-up for PB5 differs from the

other signals in port B.

Host Reset

Extend Logic

Figure 107. KBRST Generation Scheme

HRSTOB bit (MSWCTL1)

HRAPU bit (MSWCTL3) =1

VCC Power-Up Reset

IOPB6

Logic

LPFTO bit (MSWCLT3) =1

LPCPD = 0

LPC Transaction Detected

KBRST

PC87591L Datasheet(PDF) 322 Page - National Semiconductor (TI)

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