DS2155 datasheet(175/262 Pages) DALLAS

175 / 262 page

DS2156

175 of 262

24.5.3

Transmit Processing

The DS2156 can optionally insert a valid HEC byte in the cell header, or it can be programmed to

transparently transmit the HEC byte from ATM layer. When inserting a valid HEC byte, COSET (0x55)

addition can be optionally disabled. The generator polynomial used is 1 + X + X2 + X8. For

idle/unassigned cell insertion (used for cell-rate decoupling), the DS2156 inserts a valid HEC byte with or

without COSET addition, depending on the TCRDS bit (U_TCR1.3). The DS2156 can optionally

scramble payload bytes, depending on the TPSE bit (U_TCR1.4) register bit. The polynomial used for

scrambling is X43 + 1. For debugging purposes, the DS2156 can be configured to introduce a single-bit

HEC error in the cell header of cells transmitted in a controlled manner. If configured in HEC error-

insertion mode, it inserts HEC errors in HEC ON PERIOD number of cells and turns off HEC error

insertion for HEC OFF PERIOD number of cells set in the transmit HEC error-pattern register

(U_THEPR). This process repeats periodically, until HEC error insertion is disabled through U_TCR1.1.

Figure 24-6. Transmit Cell Flow

UTOPIA II

Data Input

Transmit

FIFO

HEC Insertion

ON/OFF

HEC Insertion

Payload

Scrambling

ON/OFF

HEC Error

Insertion

ON/OFF

Idle

Cell

Unassigned

Cell

Tx_Crd_sel

Tx_Coset_enb

HEC_insert_enb

Tx_Coset_enb

Scrambling_enb

HEC_err_insert_enb

HEC_ON_period

HEC_OFF_period

Cell Data

to Framer (PHY)

DS2155 Datasheet(PDF) 175 Page - Dallas Semiconductor

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