DS2155 datasheet(177/262 Pages) DALLAS

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DS2156

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The persistence of an out-of-cell delineation (OCD) event is integrated into loss-of-cell delineation

(LCD), based on programmable integration time period (receive LCD integration-period register). If OCD

persists for the programmed time, LCD is declared. LCD is deasserted only when cell delineation persists

in SYNC for the same programmed time. Whenever there is a change in LCD status, namely “into LCD”

or “out of LCD,” an external interrupt is optionally generated by the microprocessor interface based on

the corresponding mask bit U_RCR2.4. The persistence is checked every system clock period divided by

16,383. The default value of receive LCD integration period register provides an integration time of

102ms in E1 mode and 135ms in T1 mode.

If a single-bit header-error correction is enabled, the receiver mode of operation state machine follows the

state machine given in Figure 24-8. Single-bit correction is done only if correction is enabled and the state

machine is in “correction mode” of operation at the start-of-cell transfer. Receiver mode of operation is

valid only when cell delineation is in SYNC state. 8-bit correctable and 12-bit uncorrectable HEC-errored

cell counters are maintained as saturating counters.

Figure 24-8. Header Correction State Machine

No error detected

(no action)

Correction

mode

Detection

mode

Single bit error detected

(correction)

Error detected

(cell discarded)

No error

detected

(no action)

Multi-bit error

detected

(cell discarded)

HEC error correction is accomplished based on the receiver mode of operation. In correction mode, only

single-bit errors can be corrected and the receiver switches to detection mode. In detection mode, all cells

with detected header errors are discarded, provided the U_RCR1.3 bit is set = 0. When a header is

examined and found not to be in error, the receiver switches to correction mode. The term “no action” in

Figure 24-8 means no correction is performed and no cell is discarded.

The payload bytes of the cell are optionally descrambled using the self-synchronizing descrambler

polynomial X43 + 1, as given in [4]. The descrambling can be enabled through the U_RCR1.2 bit.

Descrambling is activated if cell delineation is in PRESYNC or SYNC state. The cell header is not

affected by descrambling.

After descrambling and single-bit header-error correction, the cells are written into the receive FIFO as

long as cell delineation is in SYNC and the receive FIFO is not full. Idle and/or unassigned cells can be

optionally filtered by properly programming the receive control register bits. Uncorrectable HEC-errored

cells are normally filtered and are not written into the receive FIFO unless U_RCR1.3 is set. Note that if

DS2155 Datasheet(PDF) 177 Page - Dallas Semiconductor

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