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DS2155 Datasheet(PDF) 180 Page - Dallas Semiconductor |
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DS2155 Datasheet(HTML) 180 Page - Dallas Semiconductor |
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180 / 262 page ![]() DS2156 180 of 262 An example for the receive direction is shown in Figure 24-11. The status signals UR-CLAVx are associated to PHY port addresses #4, #3, #2, and #1. There is no need for a unique null device so “X = don’t care” on the address lines UR-ADDRx. In Figure 24-11, the polling of PHY ports starts while no cell transfer takes place. The ATM layer monitors all four status signals UR-CLAVx. At clock edge #3 it detects a cell available at PHY port #1, UR-CLAV(1) asserted. It selects that PHY port by placing address #1 on the address lines with rising clock edge #3. PHY port #1 detects this at clock edge #4. At clock edge #5, PHY port #1 detects UR-ENB asserted, thus cell transfer for PHY port #1 starts with rising clock edge #5. At clock edge #5 the ATM layer detects a cell available at PHY port #3, UR-CLAV(3) asserted. Not knowing whether PHY port #1 may have another cell available or not, the ATM layer deselects PHY port #1 and selects PHY port #3 for cell transfer with rising clock edge #57 by placing address #3 on the address lines and deasserting UR-ENB. PHY port #1 and PHY port #3 detect this at clock edge #58. At clock edge #59, PHY port #3 detects UR-ENB asserted, thus cell transfer starts with rising clock edge #59. At clock edge #111, no cell is available at PHY ports #1, #2, and #4. The ATM layer keeps UR-ENB asserted and detects at clock edge #113 the first byte of another cell available from PHY port #3, UR-CLAV(3) asserted. Thus, cell transfer takes place starting with rising clock edge #112. At clock edge #164, again, no cell is available at PHY ports #1, #2, and #4. The ATM layer keeps the UR-ENB asserted and also detects at clock edge #166 no cell available from PHY port #3, UR-CLAV(3) deasserted. Thus, the ATM layer deselects PHY port #3 by deasserting UR-ENB with rising clock edge #166. Figure 24-11. Example of Direct Status Indication, Receive Direction 1 2 3 4 5 6 58 59 60 112 113 UR-CLK UR-ADDRx UR-CLAV(1) UR-ENB UR-SOC 114 H1 H1 P48 H1 UR-DATAx X 1 X UR-CLAV(2) UR-CLAV(3) UR-CLAV(4) PORT #1 PORT #2 PORT #3 PORT #4 P48 H2 57 165 166 167 111 164 3 X X X P48 X Cell Transfer (port #1) Cell Transfer (port #3) Cell Transfer (port #3) |
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