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DS2155 Datasheet(PDF) 184 Page - Dallas Semiconductor |
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DS2155 Datasheet(HTML) 184 Page - Dallas Semiconductor |
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184 / 262 page  DS2156 184 of 262 Register Name: U_TCR1 Register Description: UTOPIA Transmit Control Register 1 Register Address: 56h Bit # 7 6 5 4 3 2 1 0 Name — — — TPSE TCRDS TCAE THEIE THIE Default 0 0 0 0 0 1 0 1 Bit 0/Transmit HEC-Insertion Enable (THIE) 0 = HEC byte as received from ATM layer is transparently passed 1 = proper HEC value is computed and inserted in the HEC byte of the cell Bit 1/Transmit HEC Error-Insertion Enable (THEIE) 0 = HEC error insertion disabled 1 = HEC errors introduced in the transmitted cells as specified by transmit HEC error-insertion pattern register Bit 2/Transmit COSET-Addition Enable (TCAE) 0 = no COSET addition 1 = COSET (0x55) addition to the calculated HEC Note that if HEC insertion is disabled, then the HEC byte is transmitted transparently (this bit does not impact ATM layer cells). However, the HEC byte of idle/unassigned cells used for cell-rate decoupling includes COSET addition as long as the TCAE bit is enabled. Bit 3/Transmit Cell-Rate Decoupling Selection (TCRDS) 0 = idle cell 1 = unassigned cell Bit 4/Transmit Payload-Scrambling Enable (TPSE) 0 = disabling scrambling 1 = enabling scrambling Bits 5 to 7/Unassigned, must be set to 0 for proper operation |
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