DS2155 datasheet(186/262 Pages) DALLAS

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DS2156

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U_RLCDIP

UTOPIA Receive LCD Integration Period Register

61h

Bit #

Name

RLIP7

RLIP6

RLIP5

RLIP4

RLIP3

RLIP2

RLIP1

RLIP0

Default

Bits 0 to 7/Receive LCD Integration Period (RLIP0 to RLIP7)

This 8-bit register holds the LCD integration period value for which the out-of-cell delineation condition must

persist for declaring loss-of-cell delineation (LCD). For deasserting LCD, cell delineation should persist in the

SYNC state for the same amount of time programmed in this register. LCD state change condition can be

programmed to generate an external interrupt through U_RCR2.4. A value of 0 programmed into this register

declares LCD for every OCD condition at the resolution of the internal system clock period. The internal system

clock is 8x the line clock [16.383MHz (E1 mode) and 12.352MHz (T1 mode)].

IT = Integration Time in ms

For E1 mode, register value = IT / 1ms

For T1 mode, register value = IT / 1.326ms

For example, in E1 mode a register value of 64h (100) generates a 100ms integration time. In T1 mode, a register

value of 4Bh (75) generates a 100ms integration time.

U_RPCE

UTOPIA Receive PMON-Counter Enable Register

62h

Bit #

Name

—

Default

Bits 0 to 7/The host should always write 0x00 to this register when latching the receive PMON counter.

This register is provided for latching all receive PMON-counter values, namely the 16-bit receive assigned cell-

count value, 12-bit receive uncorrectable HEC-count value, and 8-bit receive correctable HEC-count value of a port

into the common receive assigned cell-counter latch register, receive uncorrectable HEC-counter latch register, and

receive correctable HEC-count latch register, respectively. A write into this register clears the receive PMON

counters for that port.

DS2155 Datasheet(PDF) 186 Page - Dallas Semiconductor