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DS2155 Datasheet(PDF) 190 Page - Dallas Semiconductor

Part # DS2155
Description  T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface
PDF  262 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS2155 Datasheet(HTML) 190 Page - Dallas Semiconductor

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DS2156
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Register Name:
U_RCR1
Register Description:
UTOPIA Receive Control Register 1
Register Address:
69h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
RUCFE
RICFE
RPHEC
RDE
RHECE
RCSE
Default
0
0
0
0
0
0
0
1
Bit 0/Receive COSET Subtraction Enable (RCSE)
0 = DS2156 does not do COSET subtraction from the HEC byte for checking HEC
1 = DS2156 subtracts COSET polynomial (0 x 55) from the HEC byte for checking HEC
Bit 1/Receive HEC-Error Correction Enable (RHECE)
0 = single-bit HEC-error correction is disabled
1 = DS2156 corrects single-bit HEC errors based on the current state of receiver mode of operation. Single-
bit error correction is done only if this bit is set and receiver mode of operation is in CORRECTION state.
Bit 2/Receive Descrambling Enable (RDE)
0 = payload descrambling is disabled
1 = payload descrambling is enabled. Payload of cells received in PRESYNC and SYNC state of cell
delineation are descrambled based on the self-synchronizing polynomial X43 + 1. Cell header is unaffected
by descrambling.
Bit 3/Receive Pass HEC-Errored Cells (RPHEC)
0 = DS2156 passes only error-free and error-corrected cells to ATM layer
1 = DS2156 passes all cells including HEC-errored cells, received when cell delineation is SYNC to ATM
layer
Bit 4/Receive Idle Cell-Filter Enable (RICFE)
0 = DS2156 does not filter idle cells
1 = DS2156 filters all idle cells received from being written into receive FIFO. The cell header of idle cell
(first five bytes) is 0x00, 0x00, 0x00, 0x01 and proper HEC byte. Cell payload is not considered for idle
cell filtering.
Bit 5/Receive Unassigned Cell-Filter Enable (RUCFE)
0 = DS2156 will NOT filter unassigned cells.
1 = DS2156 filters all unassigned cells received from being written into receive FIFO. The cell header of
unassigned cell (first five bytes) is 0x00, 0x00, 0x00, 0x00, and proper HEC byte. Cell payload is not
considered for unassigned cell filtering
Bits 6, 7/Unassigned, must be set to 0 for proper operation



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