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DS2155 Datasheet(PDF) 189 Page - Dallas Semiconductor |
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DS2155 Datasheet(HTML) 189 Page - Dallas Semiconductor |
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189 / 262 page  DS2156 189 of 262 Register Name: U_RSR Register Description: UTOPIA Receive Status Register Register Address: 68h Bit # 7 6 5 4 3 2 1 0 Name — — CDS1 CDS0 RMS LCDS LCDCSIS FOIS Default 0 0 0 0 0 1 0 0 Bit 0/Receive FIFO Overrun Interrupt Status (FOIS). Set if the receive FIFO overruns provided RxFIFO overrun interrupt mask bit (U_RCR2.3) is set. This bit is reset when read. Bit 1/LCD Change-of-State Interrupt Status (LCDCSIS). Set by hardware if LCD status changes, provided that the LCD interrupt-mask bit (U_RCR2.4) is set. The LCDS bit indicates the current status of LCD. This bit is reset when read. Bit 2/LCD Status (LCDS) 0 = in-cell delineation 1 = loss-of-cell delineation Bit 3/Receiver Mode Status (RMS). This bit shows valid status only when HEC correction is enabled. 0 = correction mode 1 = detection mode Bits 4, 5/Cell Delineation Status 0 to 1 (CDS0 to CDS1). Bit 5 indicates instantaneous OCD status. CDS1 CDS0 Cell Delineation Status 0 0 HUNT State 0 1 PRESYNC State 1 x SYNC State Bits 6, 7/Unused Once a read cycle to this register is detected, the interrupt status bits are cleared. If any of the lower two bits is set, the external interrupt signal is asserted. If both the bits are 0 for all the ports, the external interrupt signal is de- asserted. |
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