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DS2155 Datasheet(PDF) 183 Page - Dallas Semiconductor |
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DS2155 Datasheet(HTML) 183 Page - Dallas Semiconductor |
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183 / 262 page ![]() DS2156 183 of 262 Register Name: U_TIUPB Register Description: UTOPIA Transmit Idle/Unassigned Payload Byte Register Register Address: 54h Bit # 7 6 5 4 3 2 1 0 Name TIUP7 TIUP6 TIUP5 TIUP4 TIUP3 TIUP2 TIUP1 TIUP0 Default 0 1 1 0 1 0 1 0 Bits 0 to 7/Transmit Idle/Unassigned Payload (TIUP0 to TIUP7). Holds the payload byte to be carried in octets of idle/unassigned cells, transmitted towards line for cell rate decoupling. Register Name: U_THEPR Register Description: UTOPIA Transmit HEC Error-Insertion Pattern Register Register Address: 55h Bit # 7 6 5 4 3 2 1 0 Name HOFFP4 HOFFP3 HOFFP2 HOFFP1 HOFFP0 HONP2 HONP1 HONP0 Default 0 0 1 0 1 0 0 1 Bits 0 to 2/HEC On Period (HONP0 to HONP2). Holds the number of cells in which incorrect HEC is sent if HEC error insertion is enabled. Bits 3 to 7/HEC Off Period (HOFFP0 to HOFFP4). Holds the number of cells in which correct HEC is sent if HEC error insertion is enabled. If HEC error insertion in the transmit control register is enabled for a port, then for the HEC off period cells are transmitted to the port with correct HEC. For the HEC on period, cells are sent with incorrect HEC. This cycle repeats until HEC error insertion is disabled. Note that HEC error is introduced in all transmitted cells based on the transmit HEC error-insertion pattern register, if the HEC error-insertion bit in the transmit control register is enabled irrespective of whether the HEC insertion bit in the transmit control register is enabled or disabled. |
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