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DS2155 Datasheet(PDF) 176 Page - Dallas Semiconductor |
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DS2155 Datasheet(HTML) 176 Page - Dallas Semiconductor |
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176 / 262 page ![]() DS2156 176 of 262 24.6 Receive Operation The receive interface of the DS2156 is fully compliant with the ATM Forum’s UTOPIA Level 2 specifications [3]. The DS2156 can be configured to use any address in the range 0 to 31 as its UTOPIA port addresses. If the receive FIFO is not empty, the cell-available signal is asserted. After cell transfer from a port, the external cell-available signal updates based on the receive FIFO fill level only after one- clock cycle from cell-transfer completion. During this one-clock cycle, cell available indication for this port is kept in the deasserted state. One-clock minimum latency between two cell transfers from the same UTOPIA port is needed by the DS2156 to update its internal cell pointers. 24.6.1 Receive Processing The received bits, after ignoring framing overhead bits, are checked for possible HEC pattern. The polynomial used for HEC check is G(X) = 1 + X + X2 + X8, as recommended in [4]. The COSET subtraction (0x55) can be optionally disabled by clearing the register bit U_RCR1.0. The cell boundaries in the incoming bit stream are identified based on HEC. Figure 24-7 shows the cell- delineation state machine. The cell-delineation state machine is initially in HUNT state. In HUNT state, it performs bit-by-bit hunting for correct HEC. If correct HEC is found, it transitions to the PRESYNC state where it cell-by-cell checks for correct HEC patterns. If DELTA consecutive correct patterns are received in PRESYNC, the cell-delineation state machine transits to SYNC state. Otherwise, it goes to HUNT state itself and starts bit-by-bit hunting. In SYNC state, if ALPHA consecutive incorrect HEC patterns are received, cell delineation is lost and it goes to HUNT state. In PRESYNC and SYNC states, only cell-by- cell checking for proper HEC pattern is performed. ALPHA and DELTA are 7 and 6, respectively. Figure 24-7. Cell-Delineation State Diagram HUNT SYNC PRESYNC ALPHA consecutive incorrect HEC Incorrect HEC Correct HEC Bit by bit DELTA consecutive correct HEC Cell by cell Cell by cell |
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