MCP19124 datasheet(153/236 Pages) MICROCHIP

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 2016 Microchip Technology Inc.

DS20005619A-page 153

MCP19124/5

27.0 ENHANCED PWM MODULE

The PWM module implemented on the MCP19124/5 is

a scaled-down version of the Capture/Compare/PWM

(CCP)

module

found

standard

mid-range

microcontrollers. The module only features the PWM

module, which is slightly modified from standard

mid-range microcontrollers. In the MCP19124/5, the

PWM module is used to generate the system clock or

system oscillator. This system clock can control the

MCP19124/5 switching frequency, as well as set the

maximum allowable duty cycle. The PWM module

does not continuously adjust the duty cycle to control

the output voltage. This is accomplished by the analog

control loop and associated circuitry.

27.1

Standard Pulse-Width Modulation

Mode

The CCP will only function in PWM mode. The PWM

signal is used to set the operating frequency and

maximum allowable duty cycle of the MCP19124/5.

Figure 27-2 is a snippet of the MCP19124/5 block

diagram showing the PWM signal from the CCP

module.

FIGURE 27-1:

MCP19124/5 SNIPPET

SHOWING SYSTEM

CLOCK FROM PWM

MODULE

There are two modes of operation that concern the

system clock PWM signal. These modes are

Stand-Alone (nonfrequency synchronization) and

Frequency Synchronization.

27.1.1

STAND-ALONE (NON-FREQUENCY

SYNCHRONIZATION) MODE

When the MCP19124/5 is running stand-alone, the

PWM signal functions as the system clock. It is

operating at the programmed switching frequency with

a programmed maximum duty cycle (DCLOCK). The

programmed maximum duty cycle is not adjusted on a

cycle-by-cycle basis to control the MCP19124/5

system output. The required duty cycle (DPDRVON) to

control the output is adjusted by the MCP19124/5

analog control loop and associated circuitry. DCLOCK

does however set the maximum allowable DPDRVON.

EQUATION 27-1:

27.1.2

SWITCHING FREQUENCY

SYNCHRONIZATION MODE

The MCP19124/5 can be programmed to be switching

frequency MASTER or SLAVE devices. The MASTER

device functions as described in Section 27.1.1

“Stand-Alone (Non-Frequency Synchronization)

Mode” with the exception of the system clock also

being applied to GPA1.

A SLAVE device will receive the MASTER system

clock on GPA1. This MASTER system clock will be

OR’d with the output of the TIMER2 module. This

OR’d signal will latch PWMRL into PWMRH and

PWMPHL into PWMPHH.

Figure 27-2 shows a simplified block diagram of the

CCP module in PWM mode.

The PWMPHL register allows for a phase shift to be

added to the SLAVE system clock.

It is desired to have the MCP19124/5 SLAVE device’s

system clock start point shifted by a programmed

amount from the MASTER system clock. This SLAVE

phase shift is specified by writing to the PWMPHL

using Equation 27-1.

EQUATION 27-1:

PWM

OVE

116

PWM signal from CCP

BUCK

CLOCK

–



SLAVE

PHASE SHIFT

PWMPHL

OSC

PRESCALE VALUE





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