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MCP19124 Datasheet(PDF) 172 Page - Microchip Technology

Part # MCP19124
Description  Digitally-Enhanced Power Analog Synchronous Low-Side Dual-Loop PWM Controller
PDF  236 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP19124 Datasheet(HTML) 172 Page - Microchip Technology

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MCP19124/5
DS20005619A-page 172
 2016 Microchip Technology Inc.
28.4.5
SLAVE MODE 10-BIT ADDRESS
RECEPTION
This section describes a standard sequence of events
for the MSSP module configured as an I2C Slave in
10-bit Addressing mode.
Figure 28-12 is used as a visual reference for this
description.
This is a step-by-step process of what must be done
by slave software to accomplish I2C communication:
1.
Bus starts idle.
2.
Master sends Start condition; S bit in the
SSPSTAT register is set; SSPIF is set if interrupt
on Start detect is enabled.
3.
Master sends matching high address with R/W
bit clear; UA bit in the SSPSTAT register is set.
4.
Slave sends ACK and SSPIF is set.
5.
Software clears the SSPIF bit.
6.
Software reads received address from SSPBUF,
clearing the BF flag.
7.
Slave loads low address into SSPADD,
releasing SCL.
8.
Master sends matching low-address byte to the
Slave; UA bit is set.
9.
Slave sends ACK and SSPIF is set.
10. Slave clears SSPIF.
11. Slave reads the received matching address
from SSPBUF, clearing BF.
12. Slave loads high address into SSPADD.
13. Master clocks a data byte to the slave and
clocks out the slave’s ACK on the 9th SCL pulse;
SSPIF is set.
14. If SEN bit in the SSPCON2 register is set, CKP
is cleared by hardware and the clock is
stretched.
15. Slave clears SSPIF.
16. Slave reads the received byte from SSPBUF,
clearing BF.
17. If SEN is set, the slave sets CKP to release the
SCL.
18. Steps 13–17 are repeated for each received
byte.
19. Master sends Stop to end the transmission.
28.4.6
10-BIT ADDRESSING WITH
ADDRESS OR DATA HOLD
Reception using 10-bit addressing with AHEN or
DHEN set is the same as with 7-bit modes. The only
difference is the need to update the SSPADD register
using the UA bit. All functionality, specifically when the
CKP bit is cleared and the SCL line is held low, is the
same. Figure 28-13 can be used as a reference of a
slave in 10-bit addressing with AHEN set.
Figure 28-14 shows a standard waveform for a slave
transmitter in 10-bit Addressing mode.
Note: Updates to the SSPADD register are not
allowed until after the ACK sequence.
Note: If the low address does not match, SSPIF
and UA are still set so that the slave
software can set SSPADD back to the high
address. BF is not set because there is no
match. CKP is unaffected.



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