THCV231 datasheet(7/56 Pages) THINE

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THCV231_THCV236_Rev.2.30_E

THine Electronics, Inc.

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D25/GPIO4

D25 : Pixel Data Output

GPIO4 : General Purpose Input/Output when SUBMODE=0,

MSSEL=1 and RXDEFSEL=0.

When GPIO4 is used as Open-Drain Output, it must be connected

with a pull-up resistor to VDD. When GPIO4 is used as push pull

output or input, no external component is required.

D24/GPIO3

D24 : Pixel Data Output

GPIO3 : General Purpose Input/Output when SUBMODE=0,

MSSEL=1 and RXDEFSEL=0.

When GPIO3 is used as Open-Drain Output, it must be connected

with a pull-up resistor to VDD. When GPIO3 is used as push pull

output or input, no external component is required.

D23-D0

21-24,27-31,33-39,

42-47,52,53

Pixel Data Output

DE Output

HSYNC

HSYNC Output

VSYNC

VSYNC Output

Output Enable

0 : LVCMOS Output Disable (Hi-Z) except for HTPDN,

LOCKN when PDN1=0 and except for BETOUT when BET=1

1 : LVCMOS Output Enable

BET

Field BET entry

0 : Normal Operation

1 : Field BET Operation

RF/BETOUT

RF : Output Clock Triggering edge select. See Figure 16.

0 : Falling Edge

1 : Rising Edge

BETOUT : Field BET Result Output

RXDEFSEL

Internal Register Default Setting Select. See Table 35, Table 36

0 : for THCV231

1 : for THCV235

LFSEL

Low Frequency mode select

0 : Low Frequency mode Disable

1 : Low Frequency mode Enable

Forbid setting 1 when connecting with THCV231.

PDN1

Sub-Link Power Down

0 : Power Down. Main-Link setting by external pin

1 : Normal Operation. Main-Link Setting by 2-wire serial I/F

PDN0

Main-Link Power Down

0 : Power Down

1 : Normal Operation

TEST2

Test pin. Must be tied to Ground for normal operation.

TEST1

Test pin. Must be tied to Ground for normal operation.

CAPOUT

PWR Decoupling Capacitor Pin, 1.2V output.

CAPINA

PWR Reference Input for Analog Circuit. Must be tied to CAPOUT.

VDD

49,41,32,25,16

PWR 1.7-3.6V Digital Power Supply Pin for LVCMOS I/O

AVDD

PWR 1.7-3.6V Analog Power Supply Pin for LDO

EXPGND

GND Exposed Pad Ground. Must be tied to the PCB ground plane

through an array of vias.

CI : CML Input buffer , CB : CML Bi-directional buffer

I : LVCMOS Input buffer , IL : Low Speed LVCMOS Input buffer , O: LVCMOS Output buffer

B : LVCMOS Bi-directional buffer , BO : Open-Drain LVCMOS Bi-directional buffer

PWR : Power supply , GND : Ground

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