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THCV231 Datasheet(PDF) 22 Page - THine Electronics, Inc. |
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THCV231 Datasheet(HTML) 22 Page - THine Electronics, Inc. |
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22 / 56 page ![]() THCV231_THCV236_Rev.2.30_E Copyright©2016 THine Electronics, Inc. THine Electronics, Inc. 22/56 Security E Read/Write access to remote side 2-wire serial slave devices connected to Sub-Link Slave Device HOST MPU can access to remote side 2-wire serial slave register via Sub-Link Master and Sub-Link Slave by Sub-Link Master register settings. Sub-Link Slave has 2-wire serial master block. Up to 8 devices are connectable to 2-wire serial master of Sub-Link Slave device. Sub-Link Block 2-wire Slave Sub-Link Master Sub-Link Master Device Sub-Link Slave Device Sub-Link Block Sub-Link Slave 2-wire Master Sub-Link line I2C Slave Device#7 ・ ・ I2C Slave Device#0 LOCKN/ MSSEL=0 AIN1,AIN0 = User Select Interrupt signal Host MPU SD1(SCL) SD0(SDA) INT Register (Address 0x00 – 0x7F) Register (Address 0x80 – 0xFF) SCL SDA Figure 10. Host to 2-wire serial Slave devices connected to Sub-Link Slave device access configuration Table 21. Remote side 2-wire serial slave register Write Procedure for 8bit register address Step Description R/W Address 1 Set slave address of remote side 2-wire serial slave device (Low-order 7bits), and enable this address (High-order 1bit). W 0x04-0x0B 2 Write 1 or 0 and clear(auto clear) access status register (2WIRE_ACS_END_INT). W 0x02 bit7 3 Set the data for remote side 2-wire serial slave to write (Max 16byte). W 0x10-0x1F 4 Set slave address of access target 2-wire serial slave (choose the value set in 0x04-0x0B[6:0]), and set 0 to 0x20 bit7. W 0x20 5 Set the byte number written to remote side 2-wire serial slave (Max 16byte). (Byte number = register value + 1) W 0x21 6 Set the start address of remote side 2-wire serial slave register to write. W 0x23 7 Write 1 to WR_START_8B. (Start write access to remote side 2-wire serial slave register) W 0x25 (*1) 8 (*2) 2-wire serial slave of Sub-Link Master perform clock stretching until remote side 2-wire serial slave register access is completed. - - 8 (*3) When write access is completed, 2WIRE_ACS_END_INT register value become 1 and interrupt occurs (INT=H → L). - - 9 If wire access was normally ended, read value should be “0x1”. R 0x02 10 Repeat from step2 to step9 if needed. - - *1 It’s Prohibit that HOST MPU start access to Sub-Link Slave or remote 2-wire serial slave before the previous access to Sub-Link Slave or remote side 2-wire serial slave is completed. *2 When 2WIRE_MODE = 00 (Clock Stretching Mode) *3 When 2WIRE_MODE = 01 (No Clock Stretching Mode) |
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