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THCV231 Datasheet(PDF) 34 Page - THine Electronics, Inc. |
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THCV231 Datasheet(HTML) 34 Page - THine Electronics, Inc. |
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34 / 56 page  THCV231_THCV236_Rev.2.30_E Copyright©2016 THine Electronics, Inc. THine Electronics, Inc. 34/56 Security E Table 34. THCV231 Main-Link Control Register Map Address (Hex) Bit# R/W Default (Hex) Name Description Note Sub-Link Slave 0xD0 7 RW 1 MAINMODE MAINMODE setting 0: Forbidden 1: Sync Free Mode - 6 RW 1 HFSEL HFSEL setting 0: High Frequency Mode Disable 1: High Frequency Mode Enable - 5 RW 0 COL1 COL1 setting Data Width Setting. See Table 15. - 4 RW 1 COL0 COL0 setting Data Width Setting. See Table 15. - 3 RW 0 PRE PRE setting 0: Pre-Emphasis Disable 1: Pre-Emphasis Enable (*1) 2:1 RW 0x2 CMLDRV CMLDRV setting 00: 400mV diff p-p 01: 600mV diff p-p 10: 800mV diff p-p 11: Reserved (Forbidden) 0 RW 0 Reserved - 0xD1 7:6 R 0x0 Reserved - 5 RW 0 SSEN SSEN setting 0: SSCG Disable 1: SSCG Enable (*2) 4:0 RW 0x05 SPREAD SSCG modulation depth setting Spread depth = ±SPREAD x 0.1% (Center Spread) 0xD2 7:4 R 0x0 Reserved - 3:0 RW 0xD FMOD SSCG Modulation Frequency Setting - 0xD3 7:2 R 0x00 Reserved - 1 RW 0 BET Field BET Mode Enable setting 0: Normal Mode 1: Field BET Operation - 0 RW 0 BET_SEL Main-Link / Sub-Link Field BET Mode select 0: Main-Link Field BET Mode 1: Sub-Link Field BET Mode - 0xD4 7 R 0 Reserved - 6:0 RW 0x3E Reserved. Must be default setting. - 0xD5-0xEC 7:0 RW 0x00 Reserved - 0xED 7:3 R 0x00 Reserved - 2:0 RW 0x1 Reserved - 0xEE 7:1 R 0x00 Reserved - 0 RW 1 Reserved. Must be 1 - 0xEF 7:0 R 0x00 Reserved - 0xF0 7:2 R 0x00 Reserved - 1 RW 0 Reserved. Must be 0 - 0 RW 0 PLL_SET_EN SSCG PLL setting register Enable 1: Enable 0: Disable - 0xF1 -0xF5 7:0 R 0x00 Reserved - 0xF6 7:6 R 0x0 Reserved - 5:0 RW 0xXX PLL_SET0 SSCG PLL setting (*3) 0xF7 7:4 R 0x0 Reserved - 3:0 RW 0x0 Reserved. Must be default setting. - 0xF8 7:0 RW 0xXX PLL_SET1 SSCG PLL setting (*3) 0xF9-0xFB 7:0 RW 0x00 Reserved. Must be default setting. - 0xFC 7:6 R 0x0 Reserved - 5:0 RW 0xXX PLL_SET2 SSCG PLL setting (*3) 0xFD-0xFF 7:0 RW 0xXX Reserved. Must be default setting. - *1 See Table 4 *2 SSEN=1 and SPREAD=0 setting is forbidden *3 See Table 8, Table 16 |
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