SLMA002 datasheet(13/55 Pages) TI1

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DELAY

ENx

farads

2 I

(1)

TPS5428x

ENx

PVDD2

PVDDx

6 mA

1.2V

Time

DELAY

PVDDx

ENx

OUTx

1.2-V

Threshold

TPS54283,, TPS54286

SLUS749C – JULY 2007 – REVISED OCTOBER 2007

An R-C connected to an ENx pin may be used to delay the turn-on of the associated output after power is

applied to PVDDx (see Figure 15). After power is applied to PVDD2, the voltage on the ENx pin slowly decays

towards ground. Once the voltage decays to approximately 1.2 V, then the output is enabled and the startup

sequence begins. If it is desired to enable the outputs of the device immediately upon the application of power to

PVDD2, then omit these two components and tie the ENx pin to GND directly.

If an R-C circuit is used to delay the turn-on of the output, the resistor value must be much less than 1.2 V / 6

µA

or 200 k

Ω. A suggested value is 51 kΩ. This resistor value allows the ENx voltage to decay below the 1.2-V

threshold while the 6-

µA bias current flows.

The capacitor value required to delay the startup time (after the application of PVDD2) is shown in Equation 1.

where:

• R and C are the timing components

• V

TH is the 1.2-V enable threshold voltage

• I

ENx is the 6µA enable pin biasing current

Other enable pin functionality is dictated by the state of the SEQ pin. (See the Output Voltage Sequencing

section.)

Figure 15. Startup Delay Schematic

Figure 16. Startup Delay with R-C on Enable

DESIGN HINT

If delayed output voltage startup is not necessary, simply connect EN1 and EN2 to

GND. This configuration allows the outputs to start immediately on valid application of

PVDD2.

If ENx is allowed to go high after the Outputx has been in regulation, the upper MOSFET shuts off, and the

output decays at a rate determined by the output capacitor and the load. The internal pulldown MOSFET remains

in the OFF state. (See the Bootstrap for N-Channel MOSFET section.)

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