SLMA002 datasheet(15/55 Pages) TI1

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5-V VOUT1

(2 V/div)

3.3-V VOUT2

(2 V/div)

T - Time - 1 ms/div

Soft Start

TPS54283,, TPS54286

SLUS749C – JULY 2007 – REVISED OCTOBER 2007

DESIGN HINT

An R-C network connected to the ENx pin may be used in addition to the SEQ pin in

sequential mode to delay the startup of the first output voltage. This approach may be

necessary in systems with a large number of output voltages and elaborate voltage

sequencing requirements. See Enable and Timed Turn On of the Outputs.

If the SEQ pin is left floating, Output 1 and Output 2 each start ratiometrically when both outputs are enabled at

the same time. Output 1 and Output 2 soft start at a rate that is determined by the respective final output

voltages and enter regulation at the same time. If the EN1 and EN2 pins are allowed to operate independently,

then the two outputs also operate independently.

Figure 19. SEQ Pin Floating

Each output has a dedicated soft start circuit. The soft start voltage is an internal digital reference ramp to one of

two noninverting inputs of the error amplifier. The other input is the (internal) precision 0.8-V reference. The total

ramp time for the FB voltage to charge from 0 V to 0.8 V is about 2.1 ms. During a soft start interval, the

TPS5428x output slowly increases the voltage to the noninverting input of the error amplifier. In this way, the

output voltage ramps up slowly until the voltage on the noninverting input to the error amplifier reaches the

internal 0.8 V reference voltage. At that time, the voltage at the noninverting input to the error amplifier remains

at the reference voltage.

NOTE:

To avoid a disturbance in the output voltage during the stepping of the digital soft

start, a minimum output capacitance of 50

µF is recommended. Also see Feedback

Loop and Inductor-Capacitor (L-C) Filter Selection Once the filter and compensation

components have been established, laboratory measurements of the physical design

should be performed to confirm converter stability.

During the soft start interval, pulse-by-pulse current limiting is in effect. If an overcurrent pulse is detected, six

PWM pulses are skipped to allow the inductor current to decay before another PWM pulse is applied. (See the

Output Overload Protection section.) There is no pulse skipping if a current limit pulse is not detected.

DESIGN HINT

If the rate of rise of the input voltage (PVDDx) is such that the input voltage is too low

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SLMA002 Datasheet(PDF) 15 Page - Texas Instruments