AD9640 datasheet(36/54 Pages) AD

36 / 54 page

AD9640

Rev. B | Page 34 of 52

dBFS = 20 log(Threshold Magnitude/213)

similarly, corresponds to the fine lower threshold bits, except

that it is asserted only if the input magnitude is less than the

value programmed in the fine lower threshold register after the

dwell time elapses. The dwell time is set by the 16-bit dwell time

value located at Address 0x10A and Address 0x10B and is set in

units of ADC input clock cycles ranging from 1 to 65,535. The

fine lower threshold register is a 13-bit register that is compared

with the magnitude at the output of the ADC. This comparison

is subject to the ADC clock latency but allows a finer, more

accurate comparison. The fine upper threshold magnitude is

defined by the following equation:

The decrement gain output works from the ADC fast detect

output pins, providing a fast indication of potential overrange

conditions. The increment gain uses the comparison at the

output of the ADC, requiring the input magnitude to remain

below an accurate, programmable level for a predefined period

before signaling external circuitry to increase the gain.

The operation of the increment gain output and the decrement

gain output is shown in Figure 67.

F_UT

F_LT

FINE UPPER THRESHOLD

FINE LOWER THRESHOLD

Figure 67. Threshold Settings for F_UT and F_LT

AD9640 Datasheet(PDF) 36 Page - Analog Devices