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AD9640

Rev. B | Page 31 of 52

DIGITAL OUTPUTS

The AD9640 output drivers can be configured to interface with

1.8 V to 3.3 V CMOS logic families by matching DRVDD to the

digital supply of the interfaced logic. The AD9640 can also be

configured for LVDS outputs using a DRVDD supply voltage

of 1.8 V.

In CMOS output mode, the output drivers are sized to provide

sufficient output current to drive a wide variety of logic families.

However, large drive currents tend to cause current glitches on

the supplies that may affect converter performance.

Applications requiring the ADC to drive large capacitive loads

or large fan-outs may require external buffers or latches.

The output data format can be selected for either offset binary

or twos complement by setting the SCLK/DFS pin when operating

in the external pin mode (see Table 15).

As detailed in the AN-877 Application Note, Interfacing to High

Speed ADCs via SPI, the data format can be selected for offset

binary, twos complement, or gray code when using the SPI control.

Table 15. SCLK/DFS Mode Selection (External Pin Mode)

Voltage at Pin

SCLK/DFS

SDIO/DCS

AGND

Offset binary (default)

DCS disabled

AVDD

Twos complement

DCS enabled (default)

Digital Output Enable Function (OEB)

The AD9640 has a flexible three-state ability for the digital output

pins. The three-state mode is enabled using the SMI SDO/OEB

pin or through the SPI interface. If the SMI SDO/OEB pin is low,

the output data drivers are enabled. If the SMI SDO/OEB pin is

high, the output data drivers are placed in a high impedance state.

This OEB function is not intended for rapid access to the data

bus. Note that OEB is referenced to the digital supplies (DRVDD)

and should not exceed that supply voltage.

When using the SPI interface, the data and fast detect outputs

of each channel can be independently three-stated by using the

output enable bar bit in Register 0x14.

TIMING

The AD9640 provides latched data with a pipeline delay of

twelve clock cycles. Data outputs are available one propagation

delay (tPD) after the rising edge of the clock signal.

The length of the output data lines and loads placed on them

should be minimized to reduce transients within the AD9640.

These transients can degrade converter dynamic performance.

The lowest typical conversion rate of the AD9640 is 10 MSPS.

At clock rates below 10 MSPS, dynamic performance can degrade.

Data Clock Output (DCO)

The AD9640 provides two data clock output (DCO) signals

intended for capturing the data in an external register. The data

outputs are valid on the rising edge of DCO, unless the DCO clock

polarity has been changed via the SPI. See Figure 2 and Figure 3

for a graphical timing description.

Table 16. Output Data Format

Input (V)

Condition (V)

Offset Binary Output Mode

Twos Complement Mode

OVR

VIN+ − VIN−

< −VREF − 0.5 LSB

00 0000 0000 0000

10 0000 0000 0000

VIN+ − VIN−

= −VREF

00 0000 0000 0000

10 0000 0000 0000

VIN+ − VIN−

= 0

10 0000 0000 0000

00 0000 0000 0000

VIN+ − VIN−

= +VREF − 1.0 LSB

11 1111 1111 1111

01 1111 1111 1111

VIN+ − VIN−

> +VREF − 0.5 LSB

11 1111 1111 1111

01 1111 1111 1111

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