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AD9640

Rev. B | Page 18 of 52

Pin No.

Mnemonic

Type

Function

Digital Inputs

SYNC

Input

Digital Synchronization Pin. Slave mode only.

Digital Outputs

D0+ (LSB)

Output

Channel A/Channel B LVDS Output Data 0—True.

D0− (LSB)

Output

Channel A/Channel B LVDS Output Data 0—Complement.

D1+

Output

Channel A/Channel B LVDS Output Data 1—True.

D1−

Output

Channel A/Channel B LVDS Output Data 1—Complement.

D2+

Output

Channel A/Channel B LVDS Output Data 2—True.

D2−

Output

Channel A/Channel B LVDS Output Data 2—Complement.

D3+

Output

Channel A/Channel B LVDS Output Data 3—True.

D3−

Output

Channel A/Channel B LVDS Output Data 3—Complement.

D4+

Output

Channel A/Channel B LVDS Output Data 4—True.

D4−

Output

Channel A/Channel B LVDS Output Data 4—Complement.

D5+

Output

Channel A/Channel B LVDS Output Data 5—True.

D5−

Output

Channel A/Channel B LVDS Output Data 5—Complement.

D6+

Output

Channel A/Channel B LVDS Output Data 6 —True.

D6−

Output

Channel A/Channel B LVDS Output Data 6—Complement.

D7+

Output

Channel A/Channel B LVDS Output Data 7—True.

D7−

Output

Channel A/Channel B LVDS Output Data 7—Complement.

D8+

Output

Channel A/Channel B LVDS Output Data 8—True.

D8−

Output

Channel A/Channel B LVDS Output Data 8—Complement.

D9+

Output

Channel A/Channel B LVDS Output Data 9—True.

D9−

Output

Channel A/Channel B LVDS Output Data 9—Complement.

D10+

Output

Channel A/Channel B LVDS Output Data 10—True.

D10−

Output

Channel A/Channel B LVDS Output Data 10—Complement.

D11+

Output

Channel A/Channel B LVDS Output Data 11—True.

D11−

Output

Channel A/Channel B LVDS Output Data 11—Complement.

D12+

Output

Channel A/Channel B LVDS Output Data 12—True.

D12−

Output

Channel A/Channel B LVDS Output Data 12—Complement.

D13+ (MSB)

Output

Channel A/Channel B LVDS Output Data 13—True.

D13− (MSB)

Output

Channel A/Channel B LVDS Output Data 13—Complement.

DCO+

Output

Channel A/Channel B LVDS Data Clock Output—True.

DCO−

Output

Channel A/Channel B LVDS Data Clock Output—Complement.

SPI Control

SCLK/DFS

Input

SPI Serial Clock/Data Format Select Pin in External Pin Mode.

SDIO/DCS

Input/Output

SPI Serial Data I/O/Duty Cycle Stabilizer in External Pin Mode.

CSB

Input

SPI Chip Select (Active Low).

Signal Monitor Ports

SMI SDO/OEB

Input/Output

Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode.

SMI SDFS

Output

Signal Monitor Serial Data Frame Sync.

SMI SCLK/PDWN

Input/Output

Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode.

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