AD9640 datasheet(44/54 Pages) AD

44 / 54 page

AD9640

Rev. B | Page 42 of 52

MEMORY MAP

READING THE MEMORY MAP TABLE

Each row in the memory map table has eight bit locations. The

memory map is roughly divided into four sections: chip configura-

tion and ID register map (Address 0x00 to Address 0x02); ADC

setup, control, and test (Address 0x08 to Address 0x25); the

channel index and transfer register map (Address 0x05 to

Address 0xFF); and digital feature control (Address 0x100 to

Address 0x11B).

Starting from the right hand column, the memory map register

in Table 25 documents the default hex value for each hex address

shown. The column with the heading Bit 7 (MSB) is the start

of the default hex value given. For example, Address 0x18, VREF

select, has a hex default value of 0xC0. This means Bit 7 = 1,

Bit 6 = 1, and the remaining bits are 0s. This setting is the default

reference selection setting. The default value uses a 2.0 V peak-

to-peak reference. For more information on this function and

others, see the AN-877 Application Note, Interfacing to High Speed

ADCs via SPI. This document details the functions controlled by

Map Register Description section.

Open Locations

All address and bit locations that are not included in Table 25

are currently not supported for this device. Unused bits of a

valid address location should be written with 0s. Writing to these

locations is required only when part of an address location is

open (for example, Address 0x18). If the entire address location

is open (for example, Address 0x13), this address location should

not be written.

Default Values

Coming out of reset, critical registers are loaded with default

values. The default values for the registers are given in the

memory map register table, Table 25.

Logic Levels

An explanation of logic level terminology follows:

•

“Bit is set” is synonymous with “Bit is set to Logic 1” or

“Writing Logic 1 for the bit.”

•

“Clear a bit” is synonymous with “Bit is set to Logic 0” or

“Writing Logic 0 for the bit.”

Transfer Register Map

Address 0x08 to Address 0x18 are shadowed. Writes to these

addresses do not affect part operation until a transfer command

is issued by writing 0x01 to Address 0xFF, setting the transfer bit.

This allows these registers to be updated internally and simulta-

neously when the transfer bit is set. The internal update takes

place when the transfer bit is set, and the bit autoclears.

Channel-Specific Registers

Some channel setup functions, such as the signal monitor

thresholds, can be programmed differently for each channel.

In these cases, channel address locations are internally duplicated

for each channel. These registers are designated in the parameter

name column of Table 25 as local registers. These local registers

can be accessed by setting the appropriate Channel A or Channel B

bits in Register 0x05. If both bits are set, the subsequent write

affects the registers of both channels. In a read cycle, only

Channel A or Channel B should be set to read one of the two

registers. If both bits are set during an SPI read cycle, the part

returns the value for Channel A. Registers designated as global

in the parameter name column of Table 25 affect the entire part

or the channel features where independent settings are not

allowed between the channels. The settings in Register 0x05

do not affect the global registers.

AD9640 Datasheet(PDF) 44 Page - Analog Devices

AD9640 Datasheet(HTML) 44 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

Datasheet Download

Link URL