AD9640 datasheet(49/54 Pages) AD

49 / 54 page

AD9640

Rev. B | Page 47 of 52

Table 26. DC Correction Bandwidth

DC Correction Control Register 0x10C[5:2]

Bandwidth (Hz)

0000

1218.56

0001

609.28

0010

304.64

0011

152.32

0100

76.16

0101

38.08

0110

19.04

0111

9.52

1000

4.76

1001

2.38

1010

1.19

1011

0.60

1100

0.30

1101

0.15

1110

0.15

1111

0.15

Bit 1—DC Correction for Signal Path Enable

Setting Bit 1 high causes the output of the dc measurement

block to be summed with the data in the signal path to remove

the dc offset from the signal path.

Bit 0—DC Correction for SM Enable

Bit 0 enables the dc correction function in the signal monitoring

block. The dc correction is an averaging function that can be

used by the signal monitor to remove dc offset in the signal.

Removing this dc from the measurement allows a more accurate

reading.

Signal Monitor DC Value Channel A (Register 0x10D and

These read-only registers hold the latest dc offset value computed

by the signal monitor for Channel A.

Signal Monitor DC Value Channel B (Register 0x10F and

These read-only registers hold the latest dc offset value computed

by the signal monitor for Channel B.

Signal Monitor SPORT Control (Register 0x111)

Bit 7—Reserved

Bit 6—RMS/MS Magnitude Output Enable

These bits enable the 20-bit rms or ms magnitude measurement

as output on the SPORT.

Bit 5—Peak Power Output Enable

Bit 5 enables the 13-bit peak measurement as output on

the SPORT.

Bit 4—Threshold Crossing Output Enable

Bit 4 enables the 13-bit threshold measurement as output on

the SPORT.

Bits[3:2]—SPORT SMI SCLK Divide

The values of these bits set the SPORT SMI SCLK divide ratio

from the input clock. A value of 0x01 sets divide by 2 (default),

a value of 0x10 sets divide by 4, and a value of 0x11 sets divide by 8.

Bit 1— SPORT SMI SCLK Sleep

Setting Bit 1 high causes the SMI SCLK to remain low when the

signal monitor block has no data to transfer.

Bit 0—Signal Monitor SPORT Output Enable

When set, Bit 0 enables the SPORT output of the signal monitor

to begin shifting out the result data from the signal monitor block.

Signal Monitor Control (Register 0x112)

Bit 7—Complex Power Calculation Mode Enable

This mode assumes I data is present on one channel and Q data

is present on the opposite channel. The result reported is the

complex power, measured as

I +

Bits[6:4]—Reserved

Bit 3—Signal Monitor RMS/MS Select

Setting Bit 3 low selects rms power measurement mode. Setting

Bit 3 high selects ms power measurement mode.

Bits[2:1]—Signal Monitor Mode

Bit 2 and Bit 1 set the mode of the signal monitor for data output

to Register 0x116 to Register 0x11B. Setting Bit 2 and Bit 1 to

0x00 selects rms/ms power output; setting these bits to 0x01

selects peak power output; and setting 0x10 or 0x11 selects

threshold crossing output.

Bit 0—Signal Monitor Enable

Setting Bit 0 high enables the signal monitor block.

Signal Monitor Period (Register 0x113 to Register 0x115)

This 24-bit value sets the number of clock cycles over which the

signal monitor performs its operation. Although this register

defaults to 64 (0x40), the minimum value for this register is 128

(0x80) cycles – writing values less than 128 can cause inaccurate

results.

AD9640 Datasheet(PDF) 49 Page - Analog Devices

AD9640 Datasheet(HTML) 49 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

Datasheet Download

Link URL