AD9640 datasheet(32/54 Pages) AD

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AD9640

Rev. B | Page 30 of 52

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 63, the power dissipated by the AD9640

is proportional to its sample rate. In CMOS output mode,

the digital power dissipation is determined primarily by the

strength of the digital drivers and the load on each output bit.

The maximum DRVDD current (IDRVDD) can be calculated as

IDRVDD = VDRVDD × CLOAD × fCLK × N

where N is the number of output bits (30 in the case of the AD9640

with the FD bits disabled). This maximum current occurs when

every output bit switches on every clock cycle, that is, a full-

scale square wave at the Nyquist frequency of fCLK/2. In practice,

the DRVDD current is established by the average number of

output bits switching, which is determined by the sample rate

and the characteristics of the analog input signal.

Reducing the capacitive load presented to the output drivers can

minimize digital power consumption. The data in Figure 63 was

taken with the same operating conditions as the Typical

Performance Characteristics, with a 5 pF load on each output

driver.

150

125

1.25

0.75

1.0

ENCODE FREQUENCY (MHz)

0.5

0.25

0.5

0.4

0.3

0.2

0.1

100

IAVDD

TOTAL POWER

IDRVDD

IDVDD

Figure 63. AD9640-150 Power and Current vs. Clock Frequency

125

1.25

0.75

1.0

ENCODE FREQUENCY (MHz)

0.5

0.25

0.5

0.4

0.3

0.2

0.1

100

IAVDD

TOTAL POWER

IDVDD

IDRVDD

Figure 64. AD9640-125 Power and Current vs. Clock Frequency

ENCODE FREQUENCY (MHz)

0.75

0.25

0.5

100

0.4

0.3

0.2

0.1

IAVDD

TOTAL POWER

IDRVDD

IDVDD

Figure 65. AD9640-105 Power and Current vs. Clock Frequency

0.75

ENCODE FREQUENCY (MHz)

0.5

0.25

0.3

0.2

0.1

IAVDD

TOTAL POWER

IDRVDD

IDVDD

Figure 66. AD9640-80 Power and Current vs. Clock Frequency

By asserting PDWN (either through the SPI port or by asserting

the PDWN pin high), the AD9640 is placed in power-down

mode. In this state, the ADC typically dissipates 2.5 mW.

During power-down, the output drivers are placed in a high

impedance state. Asserting the PDWN pin low returns the

AD9640 to its normal operational mode. Note that PDWN is

referenced to the digital supplies (DRVDD) and should not

exceed that supply voltage.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering power-

down mode and then must be recharged when returning to normal

operation. As a result, wake-up time is related to the time spent

in power-down mode, and shorter power-down cycles result in

proportionally shorter wake-up times.

When using the SPI port interface, the user can place the ADC

in power-down mode or standby mode. Standby mode allows

the user to keep the internal reference circuitry powered when

faster wake-up times are required. See the Memory Map Register

Description section for more details.

AD9640 Datasheet(PDF) 32 Page - Analog Devices

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