AD7294 datasheet(31/48 Pages) AD

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AD7294

Data Sheet

Rev. I | Page 30 of 47

DACA,DACB, DACC, DACD, REGISTERS (0x01 TO 0x04)

Writing to these register addresses sets the DACA, DACB, DACC,

and DACD output voltage codes, respectively. Bits[D11:D0] in

the write result register are the data bits sent to DACA. Bit D15

to Bit D12 are ignored.

Table 17. DAC Register (First Write)1

MSB

LSB

D15

D14

D13

D12

D11

D10

B11

B10

X is don’t care.

Table 18. DAC Register (Second Write)

MSB

LSB

ALERT STATUS REGISTER A (0x05), REGISTER B

(0x06), AND REGISTER C (0x07)

The alert status registers (A, B, and C) are 8-bit read/write

registers that provide information on an alert event. If a

conversion results in activating the ALERT/BUSY pin or the

alert_flag bit in the result register or TSENSE registers, the alert

status register can be read to gain further information. To clear

the full content of any one of the alert registers, write a code of

FF (all ones) to the relevant registers. Alternatively, the user can

write to the respective alert bit in the selected alert register to

clear the alert associated with that bit. The entire contents of all

the alert status registers can be cleared by writing a 1 to Bit D1

and Bit D2 in the configuration register, as shown in Table 24.

However, this operation then enables the ALERT/BUSY pin for

subsequent conversions. See the Alerts and Limits Theory

section for more details.

CHANNEL SEQUENCE REGISTER (0x08)

The channel sequence register is an 8-bit read/write register that

allows the user to sequence the ADC conversions to be per-

formed in autocycle mode. Table 22 shows the content of the

channel sequence register. See the Modes of Operation section

for more information.

Table 19. Alert Status Register A

Alert Bit

Function

VIN3

high alert

VIN3

low alert

VIN2

high alert

VIN2

low alert

VIN1

high alert

VIN1

low alert

VIN0

high alert

VIN0

low alert

Table 20. Alert Status Register B

Alert Bit

Function

Reserved

ISENSE2

overrange

ISENSE1

overrange

ISENSE2

high alert

ISENSE2

low alert

ISENSE1

high alert

ISENSE1

low alert

Table 21. Alert Status Register C

Alert Bit

Function

Open-diode

flag

Overtemp

alert

TSENSEINT

high alert

TSENSEINT

low alert

TSENSE2

high alert

TSENSE2

low alert

TSENSE1

high alert

TSENSE1

low alert

Table 22. Channel Sequence Register

Channel Bit

Function

Reserved

ISENSE2

ISENSE1

VIN3

VIN2

VIN1

VIN0

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