AD7294 datasheet(32/48 Pages) AD

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Data Sheet

AD7294

Rev. I | Page 31 of 47

CONFIGURATION REGISTER (0x09)

The configuration register is a 16-bit read/write register that

sets the operating modes of the AD7294. The bit functions of

the configuration register are outlined in Table 23 and Table 24.

On power-up, the configuration register is reset to 0x0000.

Sample Delay and Bit Trial Delay

It is recommended that no I2C bus activity occur when a con-

version is taking place; however, this may not be possible, for

example, when operating in autocycle mode. Bit D14 and Bit D13

in the configuration register are used to delay critical sample

intervals and bit trials from occurring while there is activity

on the I2C bus. On power-up, Bit D14 (noise-delayed sampling),

Bit D13 (noise-delayed bit trials), and Bit D3 (I2C filters) are

enabled (set to 0). This configuration is appropriate for low

frequency applications because the bit trials are prevented from

occurring when there is activity on the I2C bus, thus ensuring

good dc linearity performance. For high frequency input signals,

it may be desirable to have a known sampling point, thus the

noise-delayed sampling can be disabled by writing a 1 to Bit D14 in

the configuration register. This ensures that the sampling instance

is fixed relative to SDA, resulting in improved SNR performance. If

noise-delay samplings extend longer than 1 µs, the current

conversion terminates. This termination can occur if there are

edges on SDA that are outside the I2C specification. When noise-

delayed sampling is enabled, the rise and fall times must meet

the I2C-specified standard. When D13 is enabled, the conversion

time may vary.

The default configuration for Bit D3 (enabled) is recommended

for normal operation because it ensures that the I2C requirements

for tOf (minimum) and tSP are met. The I2C filters reject glitches

shorter than 50 ns. If this function is disabled, the conversion

results are more susceptible to noise from the I2C bus.

Table 23. Configuration Register Bit Function Description D15 to D8

Channel

Bit

D15

D14

D13

D12

D11

D10

Function

Reserved

Noise-delayed

sampling. Use to

delay critical

sample intervals

from occurring

when there is

activity on the

I2C bus.

Noise-delayed

bit trials. Use to

delay critical bit

trials from

occurring when

there is activity

on the I2C bus.

Autocycle

mode

Pseudo

differential

mode for

VIN3/VIN4

Pseudo

differential

mode for

VIN1/VIN2

Differential

mode for

VIN3/VIN4

Differential

mode for

VIN1/VIN2

Setting

Enabled = 0

Enabled = 1

Disabled = 1

Disabled = 0

Table 24. Configuration Register Bit Function Description D7 to D0

Channel

Bit

Function

2VREF range

for VIN4

2VREF range

for VIN3

2VREF range

for VIN2

2VREF range

for VIN1

I2C filters

ALERT pin

BUSY pin (D2 = 0),

clear alerts (D2 = 1)

Select ALERT

pin polarity

(active high/

active low)

Setting

Enabled = 1

Disabled = 0

Enabled = 1

Disabled = 0

Enabled = 1

Disabled = 0

Enabled = 1

Disabled = 0

Enabled = 0

Disabled = 1

Enabled

D2 = 1

D1 = 0

Disabled

D2 = 0

Enabled

D1 = 1 + D0 = 0

Disabled D1 = 0

Active high = 1

Active low = 0

Table 25. Alert/Busy Function Description

ALERT/BUSY Pin Functions

Pin does not provide any interrupt signal.

Configures pin as a busy output.

Configures pin as an alert output.

Resets the ALERT/BUSY output pin, the alert_flag bit in the conversion result register, and the entire alert status register (if any is

active). 1,1 is written to Bits[D2:D1] in the configuration register to reset the ALERT/BUSY pin, the alert_flag bit, and the alert status

register. Following this write, the contents of the configuration register read 1, 0 for Bit D2 and Bit D1, respectively, if read back.

Table 26. ADC Input Mode Example

D11

D10

Description

All channels single-ended

Differential mode on VIN1/VIN2

Pseudo differential mode on VIN1/VIN2

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